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| REJ09B0018-0200Z 8 7540 Group User's Manual RENESAS 8-BIT CISC SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 740 SERIES Before using this material, please visit our website to confirm that this is the most current document available. Rev. 2.00 Revision date: Jun 21, 2004 www.renesas.com Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 2. 3. 4. 5. 6. 7. 8. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http:// www.renesas.com). When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. REVISION HISTORY Rev. Date 7540 Group User's Manual Description Summary Page 1.00 Sep. 17, 2002 - 1.10 May 28, 2003 1-17 First edition issued [Pull-up control register] PULL; Note added. Fig.15; Note 2 eliminated. 1-19 Fig.17; (2) Ports P01,P02 revised. 1-34 Fig.29; Port P03 direction register block, Port P01 direction register block and Port P02 direction register block revised. 1-45 (3) RC oscillation revised. 2-49 Fig.2.4.12; RTI RTS 2-52 Fig.2.4.16; Prescaler X 1/4 1/2, CNTR0 pin output 4 MHz 4 kHz 2-53 Fig.2.4.17; The second CPUM setting 00000X002 11000X002 Prescaler X 0316 0116, Note 2 revised. Fig.2.4.26; The followings are revised. 2-61 The second setting of CNTR0 interrupt enable bit and Timer X interrupt enable bit. The second setting of timer X mode register. Fig.3.3.5; NOP added. 3-86 2.00 Jun. 21, 2004 All pages Words standardized: On-chip oscillator, A/D converter 1-9 Fig. 8: "Under development" eliminated. 1-10 Table 2: "Under development" eliminated. 1-11 CPU: Description revised. 1-17 [Pull-up control register] PULL: Note added 1-19 Fig.17 (2) Ports P01, P02 revised. 1-34 Fig. 29 P03/TXOUT, P01/TYOUT, P02/TZOUT revised. 1-42 Note on A/D converter added. 1-45 Fig. 49 revised. 1-51 Note on A/D converter added. 1-52 Notes on clock generating circuit: On-chip oscillator operation added. Note on Power Source Voltage, and Electrical Characteristic Difference Among Mask ROM and One Time PROM Version MCUs added. 2-5 Fig.2.1.6: Note 2 eliminated. 2-14 Fig.2.2.3: Note 2 eliminated. 2-35 2.2.7 Notes on timer A, (2): Register name revised. 2-36 Fig.2.3.2: Description revised. 2-66 Fig.2.5.7: Description revised. 2-134 2.8.4 Notes on A/D converter: (3) added. 2-145 2.9.6 Notes on oscillation stop detection circuit, (1): added. 3-82 3.3.10 Notes on A/D converter: (3) added. 3-83 3.3.11 Notes on oscillation stop detection circuit, (1): added. 3-91 3.3.19 Note on Power Source Voltage and 3.3.20 Electrical Characteristic Difference Among Mask ROM and One Time PROM Version MCUs added. (1/2) REVISION HISTORY Rev. 2.00 7540 Group User's Manual Description Summary Date Page Jun. 21, 2004 3-100 3-106 3-108 3-120 3-140 Fig.3.5.5: Note 2 eliminated. Fig.3.5.15: Description revised. Fig.3.5.19: Description revised. 32P6U-A revised. Fig.3.11.1: Memory address of 7531 Group revised. (2/2) BEFORE USING THIS MANUAL This user's manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. Chapter 3 also includes necessary information for systems development. You must refer to that chapter. 1. Organization q CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function. q CHAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of relevant registers. q CHAPTER 3 APPENDIX This chapter includes necessary information for systems development using the microcomputer, such as the electrical characteristics, the list of registers. 2. Structure of register The figure of each register structure describes its functions, contents at reset, and attributes as follows : (Note 2) Bits b7 b6 b5 b4 b3 b2 b1 b0 0 Bit attributes (Note 1) Contents immediately after reset release CPU mode register (CPUM) [Address : 3B 16] B 0 1 2 3 4 5 6 7 Stack page selection bit Name Processor mode bits b1 b0 Function 0 0 : Single-chip mode 01: 10: Not available 11: 0 : 0 page 1 : 1 page At reset RW 0 0 0 0 0 1 Nothing arranged for these bits. These are write disabled bits. When these bits are read out, the contents are "0." Fix this bit to "0." Main clock (XIN-XOUT) stop bit Internal system clock selection bit 0 : Operating 1 : Stopped 0 : XIN-XOUT selected 1 : XCIN-XCOUT selected : Bit in which nothing is arranged : Bit that is not used for control of the corresponding function Note 1:. Contents immediately after reset release 0....... "0" at reset release 1....... "1" at reset release ?....... Undefined at reset release .......Contents determined by option at reset release Note 2: Bit attributes......... The attributes of control register bits are classified into 3 bytes : read-only, writeonly and read and write. In the figure, these attributes are represented as follows : R....... Read ...... Read enabled .......Read disabled W......Write ..... Write enabled ...... Write disabled ......."0" write 3. Supplementation For details of software, refer to the "740 FAMILY SOFTWARE MANUAL." For development tools, refer to the "Renesas Technology tool Index for 740 Family." Homepage (http:/ /www.renesas.com/eng/products/mpumcu/toolhp/mcu/740_e.htm). Table of contents 7540 Group Table of contents CHAPTER 1 HARDWARE DESCRIPTION ................................................................................................................................ 1-2 FEATURES ...................................................................................................................................... 1-2 APPLICATION ................................................................................................................................ 1-2 PIN CONFIGURATION .................................................................................................................. 1-3 FUNCTIONAL BLOCK .................................................................................................................. 1-5 PIN DESCRIPTION ........................................................................................................................ 1-8 GROUP EXPANSION .................................................................................................................... 1-9 FUNCTIONAL DESCRIPTION .................................................................................................... 1-11 Central Processing Unit (CPU) ............................................................................................ 1-11 Memory .................................................................................................................................... 1-15 I/O Ports .................................................................................................................................. 1-17 Interrupts ................................................................................................................................. 1-21 Key Input Interrupt (Key-On Wake-Up) ............................................................................... 1-23 Timers ...................................................................................................................................... 1-24 Serial I/O ................................................................................................................................. 1-35 A/D Converter ......................................................................................................................... 1-41 Watchdog Timer ..................................................................................................................... 1-42 Reset Circuit ........................................................................................................................... 1-43 Clock Generating Circuit ....................................................................................................... 1-45 NOTES ON PROGRAMMING ..................................................................................................... 1-49 Processor Status Register .................................................................................................... 1-49 Interrupts ................................................................................................................................. 1-49 Decimal Calculations .............................................................................................................. 1-49 Ports ......................................................................................................................................... 1-49 A/D Conversion ....................................................................................................................... 1-49 Instruction Execution Timing ................................................................................................. 1-49 CPU Mode Register ............................................................................................................... 1-49 State Transition ...................................................................................................................... 1-49 NOTES ON HARDWARE ............................................................................................................ 1-49 Handling of Power Source Pin ............................................................................................. 1-49 One Time PROM Version ..................................................................................................... 1-49 NOTES ON PERIPHERAL FUNCTIONS .................................................................................. 1-50 s Interrupt ............................................................................................................................... 1-50 s Timers .................................................................................................................................. 1-50 s Timer A ............................................................................................................................... 1-50 s Timer X ............................................................................................................................... 1-50 s Timer Y: Programmable Generation Waveform Mode .................................................. 1-50 s Timer Z: Programmable Waveform Generation Mode .................................................. 1-50 s Timer Z: Programmable One-shot Generation Mode ................................................... 1-51 s Timer Z: Programmable Wait One-shot Generation Mode .......................................... 1-51 s Serial I/O ............................................................................................................................. 1-51 s A/D Converter ..................................................................................................................... 1-51 s Notes on Clock Generating Circuit ................................................................................. 1-52 s Notes on Power Source Volage ...................................................................................... 1-52 s Electric Characteristic Differences Among Mask ROM and One Time PROM Version MCUs .... 1-52 DATA REQUIRED FOR MASK ORDERS ................................................................................ 1-53 DATA REQUIRED FOR ROM PROGRAMMING ORDERS .................................................... 1-53 ROM PROGRAMMING METHOD .............................................................................................. 1-53 FUNCTIONAL DESCRIPTION SUPPLEMENT ......................................................................... 1-54 i Table of contents 7540 Group CHAPTER 2 APPLICATION 2.1 I/O port ..................................................................................................................................... 2-2 2.1.1 Memory map ................................................................................................................... 2-2 2.1.2 Relevant registers .......................................................................................................... 2-3 2.1.3 Application example of key-on wake up (1) ............................................................... 2-7 2.1.4 Application example of key-on wake up (2) ............................................................... 2-9 2.1.5 Handling of unused pins ............................................................................................. 2-10 2.1.6 Notes on input and output ports ................................................................................ 2-11 2.1.7 Termination of unused pins ........................................................................................ 2-12 2.2 Timer A .................................................................................................................................. 2-13 2.2.1 Memory map ................................................................................................................. 2-13 2.2.2 Relevant registers ........................................................................................................ 2-14 2.2.3 Timer mode ................................................................................................................... 2-19 2.2.4 Period measurement mode ......................................................................................... 2-22 2.2.5 Event counter mode ..................................................................................................... 2-26 2.2.6 Pulse width HL continuously measurement mode ................................................... 2-30 2.2.7 Notes on timer A .......................................................................................................... 2-35 2.3 Timer 1 ................................................................................................................................... 2-36 2.3.1 Memory map ................................................................................................................. 2-36 2.3.2 Relevant registers ........................................................................................................ 2-36 2.3.3 Timer 1 operation description ..................................................................................... 2-39 2.3.4 Notes on timer 1 .......................................................................................................... 2-39 2.4 Timer X .................................................................................................................................. 2-40 2.4.1 Memory map ................................................................................................................. 2-40 2.4.2 Relevant registers ........................................................................................................ 2-41 2.4.3 Timer mode ................................................................................................................... 2-46 2.4.4 Pulse output mode ....................................................................................................... 2-50 2.4.5 Event counter mode ..................................................................................................... 2-54 2.4.6 Pulse width measurement mode ................................................................................ 2-58 2.4.7 Notes on timer X .......................................................................................................... 2-62 2.5 Timer Y and timer Z ........................................................................................................... 2-63 2.5.1 Memory map ................................................................................................................. 2-63 2.5.2 Relevant registers ........................................................................................................ 2-64 2.5.3 Timer mode (timer Y and timer Z) ............................................................................ 2-73 2.5.4 Programmable waveform generation mode (timer Y and timer Z) ....................... 2-77 2.5.5 Programmable one-shot generation mode (timer Z) ............................................... 2-84 2.5.6 Programmable wait one-shot generation mode (timer Z) ....................................... 2-91 2.5.7 Notes on timer Y and timer Z .................................................................................... 2-99 2.6 Serial I/O1 ............................................................................................................................ 2-101 2.6.1 Memory map ............................................................................................................... 2-101 2.6.2 Relevant registers ...................................................................................................... 2-101 2.6.3 Serial I/O1 transfer data format ............................................................................... 2-105 2.6.4 Application example of clock synchronous serial I/O1 ......................................... 2-106 2.6.5 Application example of clock asynchronous serial I/O1 ....................................... 2-112 2.6.6 Notes on Serial I/O1 .................................................................................................. 2-118 2.7 Serial I/O2 ............................................................................................................................ 2-120 2.7.1 Memory map ............................................................................................................... 2-120 2.7.2 Relevant registers ...................................................................................................... 2-120 2.7.3 Application example of serial I/O2 ........................................................................... 2-123 2.7.4 Notes on serial I/O2 .................................................................................................. 2-128 2.8 A/D converter ..................................................................................................................... 2-129 2.8.1 Memory map ............................................................................................................... 2-129 2.8.2 Relevant registers ...................................................................................................... 2-129 2.8.3 A/D converter application examples ........................................................................ 2-132 2.8.4 Notes on A/D converter ............................................................................................ 2-134 ii Table of contents 7540 Group 2.9 Oscillation control ............................................................................................................. 2-135 2.9.1 Memory map ............................................................................................................... 2-135 2.9.2 Relevant registers ...................................................................................................... 2-135 2.9.3 Application example of on-chip oscillator ............................................................... 2-137 2.9.4 Oscillation stop detection circuit .............................................................................. 2-139 2.9.5 State transition ........................................................................................................... 2-142 2.9.6 Notes on oscillation stop detection circuit .............................................................. 2-145 CHAPTER 3 APPENDIX 3.1 Electrical characteristics ..................................................................................................... 3-2 3.1.1 7540 Group (General purpose) .................................................................................... 3-2 3.1.2 7540Group (Extended operating temperature version) ........................................... 3-13 3.1.3 7540Group (Extended operating temperature 125 C version) ............................. 3-22 3.2 Typical characteristics ....................................................................................................... 3-31 3.2.1 Mask ROM version ...................................................................................................... 3-31 3.2.2 One Time PROM version ............................................................................................ 3-52 3.3 Notes on use ........................................................................................................................ 3-73 3.3.1 Notes on input and output ports ................................................................................ 3-73 3.3.2 Termination of unused pins ........................................................................................ 3-74 3.3.3 Notes on Timer ............................................................................................................. 3-75 3.3.4 Notes on Timer A ........................................................................................................ 3-75 3.3.5 Notes on timer 1 .......................................................................................................... 3-75 3.3.6 Notes on Timer X ........................................................................................................ 3-76 3.3.7 Notes on timer Y and timer Z .................................................................................... 3-77 3.3.8 Notes on Serial I/O1 .................................................................................................... 3-79 3.3.9 Notes on serial I/O2 .................................................................................................... 3-81 3.3.10 Notes on A/D converter ............................................................................................ 3-82 3.3.11 Notes on oscillation stop detection circuit .............................................................. 3-83 3.3.12 Notes on CPU mode register ................................................................................... 3-85 3.3.13 Notes on interrupts .................................................................................................... 3-86 3.3.14 Notes on RESET pin ................................................................................................. 3-87 3.3.15 Notes on programming .............................................................................................. 3-88 3.3.16 Programming and test of built-in PROM version ................................................... 3-90 3.3.17 Handling of Power Source Pin ................................................................................. 3-90 3.3.18 Notes on built-in PROM version .............................................................................. 3-91 3.3.19 Notes on Power Source Voltage ............................................................................. 3-91 3.3.20 Electric Characteristic Differences Among Mask ROM and One Time PROM Version MCUs .... 3-91 3.4 Countermeasures against noise ...................................................................................... 3-92 3.4.1 Shortest wiring length .................................................................................................. 3-92 3.4.2 Connection of bypass capacitor across VSS line and VCC line ............................... 3-94 3.4.3 Wiring to analog input pins ........................................................................................ 3-95 3.4.4 Oscillator concerns ....................................................................................................... 3-95 3.4.5 Setup for I/O ports ....................................................................................................... 3-96 3.4.6 Providing of watchdog timer function by software .................................................. 3-97 3.5 List of registers ................................................................................................................... 3-98 3.6 Package outline ................................................................................................................. 3-120 3.7 Machine instructions ........................................................................................................ 3-122 3.8 List of instruction code ................................................................................................... 3-133 3.9 SFR memory map .............................................................................................................. 3-134 3.10 Pin configurations ........................................................................................................... 3-135 3.11 Differences between 7540 Group and 7531 Group ................................................. 3-139 iii List of figures 7540 Group List of figures CHAPTER 1 HARDWARE Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 1 Pin configuration (32P6U-A type) ..................................................................................... 1-3 2 Pin configuration (36P2R-A type) ..................................................................................... 1-3 3 Pin configuration (32P4B-A type) ..................................................................................... 1-4 4 Pin configuration (42S1M type) ........................................................................................ 1-4 5 Functional block diagram (32P6U package) ................................................................... 1-5 6 Functional block diagram (36P2R package) ................................................................... 1-6 7 Functional block diagram (32P4B package) ................................................................... 1-7 8 Memory expansion plan ..................................................................................................... 1-9 9 740 Family CPU register structure ................................................................................. 1-11 10 Register push and pop at interrupt generation and subroutine call ....................... 1-12 11 Structure of CPU mode register ................................................................................... 1-14 12 Switching method of CPU mode register .................................................................... 1-14 13 Memory map diagram .................................................................................................... 1-15 14 Memory map of special function register (SFR) ........................................................ 1-16 15 Structure of pull-up control register ............................................................................. 1-17 16 Structure of port P1P3 control register ....................................................................... 1-17 17 Block diagram of ports (1) ............................................................................................ 1-19 18 Block diagram of ports (2) ............................................................................................ 1-20 19 Interrupt control ............................................................................................................... 1-22 20 Structure of Interrupt-related registers ........................................................................ 1-22 21 Connection example when using key input interrupt and port P0 block diagram 1-23 22 Structure of timer A mode register .............................................................................. 1-25 23 Structure of timer X mode register .............................................................................. 1-26 24 Timer count source set register ................................................................................... 1-26 25 Structure of timer Y, Z mode register ......................................................................... 1-32 26 Structure of timer Y, Z waveform output control register ......................................... 1-32 27 Structure of one-shot start register .............................................................................. 1-32 28 Block diagram of timer 1 and timer A ......................................................................... 1-33 29 Block diagram of timer X, timer Y and timer Z ......................................................... 1-34 30 Block diagram of clock synchronous serial I/O1 ........................................................ 1-35 31 Operation of clock synchronous serial I/O1 function ................................................ 1-35 32 Block diagram of UART serial I/O1 ............................................................................. 1-36 33 Operation of UART serial I/O1 function ...................................................................... 1-36 34 Structure of serial I/O1-related registers ..................................................................... 1-38 35 Structure of serial I/O2 control registers ..................................................................... 1-39 36 Block diagram of serial I/O2 ......................................................................................... 1-39 37 Serial I/O2 timing (LSB first) ........................................................................................ 1-40 38 Structure of A/D control register .................................................................................. 1-41 39 Structure of A/D conversion register ........................................................................... 1-41 40 Block diagram of A/D converter ................................................................................... 1-41 41 Block diagram of watchdog timer ................................................................................. 1-42 42 Structure of watchdog timer control register .............................................................. 1-42 43 Example of reset circuit ................................................................................................. 1-43 44 Timing diagram at reset ................................................................................................ 1-43 45 Internal status of microcomputer at reset ................................................................... 1-44 46 External circuit of ceramic resonator ........................................................................... 1-45 47 External circuit of RC oscillation .................................................................................. 1-45 48 External clock input circuit ............................................................................................ 1-45 iv List of figures 7540 Group Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 49 50 51 52 53 54 55 56 57 58 Processing of XIN and XOUT pins at on-chip oscillator operation .............................. 1-45 Structure of MISRG ........................................................................................................ 1-46 Block diagram of internal clock generating circuit (for ceramic resonator) ........... 1-47 Block diagram of internal clock generating circuit (for RC oscillation) ................... 1-47 State transition ................................................................................................................ 1-48 Programming and testing of One Time PROM version ............................................ 1-53 Timing chart after an interrupt occurs ......................................................................... 1-55 Time up to execution of the interrupt processing routine ........................................ 1-55 A/D conversion equivalent circuit ................................................................................. 1-57 A/D conversion timing chart .......................................................................................... 1-57 CHAPTER 2 APPLICATION Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.1.1 Memory map of registers relevant to I/O port ......................................................... 2-2 2.1.2 Structure of Port Pi (i = 0, 2, 3) ................................................................................ 2-3 2.1.3 Structure of Port P1 ..................................................................................................... 2-3 2.1.4 Structure of Port Pi direction register (i = 0, 2, 3) ................................................. 2-4 2.1.5 Structure of Port P1 direction register ...................................................................... 2-4 2.1.6 Structure of Pull-up control register .......................................................................... 2-5 2.1.7 Structure of Port P1P3 control register .................................................................... 2-5 2.1.8 Structure of Interrupt edge selection register .......................................................... 2-6 2.1.9 Structure of Interrupt request register 1 ................................................................... 2-6 2.1.10 Structure of Interrupt control register 1 .................................................................. 2-7 2.1.11 Example of application circuit .................................................................................. 2-7 2.1.12 Example of control procedure (1) ............................................................................ 2-8 2.1.13 Example of control procedure (2) ............................................................................ 2-9 2.2.1 Memory map of registers relevant to timer A ........................................................ 2-13 2.2.2 Structure of Port P0 direction register .................................................................... 2-14 2.2.3 Structure of Pull-up control register ........................................................................ 2-14 2.2.4 Structure of Timer A mode register ......................................................................... 2-15 2.2.5 Structure of Timer A register .................................................................................... 2-16 2.2.6 Structure of Interrupt edge selection register ........................................................ 2-16 2.2.7 Structure of Interrupt request register 1 ................................................................. 2-17 2.2.8 Structure of Interrupt request register 2 ................................................................. 2-17 2.2.9 Structure of Interrupt control register 1 .................................................................. 2-18 2.2.10 Structure of Interrupt control register 2 ................................................................ 2-18 2.2.11 Setting method for timer mode .............................................................................. 2-20 2.2.12 Example of control procedure ................................................................................ 2-21 2.2.13 Setting method for period measurement mode (1) ............................................. 2-22 2.2.14 Setting method for period measurement mode (2) ............................................. 2-23 2.2.15 Example of peripheral circuit .................................................................................. 2-24 2.2.16 Example of control procedure ................................................................................ 2-25 2.2.17 Setting method for event counter mode (1) ......................................................... 2-26 2.2.18 Setting method for event counter mode (2) ......................................................... 2-27 2.2.19 Example of measurement method of frequency .................................................. 2-28 2.2.20 Example of control procedure ................................................................................ 2-29 2.2.21 Setting method for pulse width HL continuously measurement mode (1) ....... 2-30 2.2.22 Setting method for pulse width HL continuously measurement mode (2) ....... 2-31 2.2.23 Example of peripheral circuit .................................................................................. 2-32 2.2.24 Operation timing when ringing pulse is input ...................................................... 2-32 2.2.25 Example of control procedure (1) .......................................................................... 2-33 2.2.26 Example of control procedure (2) .......................................................................... 2-34 v List of figures 7540 Group Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.3.1 Memory map of registers relevant to timer 1 ........................................................ 2-36 2.3.2 Structure of Prescaler 1 ............................................................................................ 2-36 2.3.3 Structure of Timer 1 .................................................................................................. 2-37 2.3.4 Structure of MISRG ................................................................................................... 2-37 2.3.5 Structure of Interrupt request register 2 ................................................................. 2-38 2.3.6 Structure of Interrupt control register 2 .................................................................. 2-38 2.4.1 Memory map of registers relevant to timer X ........................................................ 2-40 2.4.2 Structure of Port P0 direction register .................................................................... 2-41 2.4.3 Structure of Port P1 direction register .................................................................... 2-41 2.4.4 Structure of Timer X mode register ......................................................................... 2-42 2.4.5 Structure of Prescaler X ............................................................................................ 2-43 2.4.6 Structure of Timer X .................................................................................................. 2-43 2.4.7 Structure of Timer count source set register ......................................................... 2-44 2.4.8 Structure of Interrupt request register 1 ................................................................. 2-45 2.4.9 Structure of Interrupt control register 1 .................................................................. 2-45 2.4.10 Setting method for timer mode .............................................................................. 2-47 2.4.11 Connection of timer and setting of division ratio ................................................ 2-48 2.4.12 Example of control procedure ................................................................................ 2-49 2.4.13 Setting method for pulse output mode (1) ........................................................... 2-50 2.4.14 Setting method for pulse output mode (2) ........................................................... 2-51 2.4.15 Example of peripheral circuit .................................................................................. 2-52 2.4.16 Connection of timer and setting of division ratio ................................................ 2-52 2.4.17 Example of control procedure ................................................................................ 2-53 2.4.18 Setting method for event counter mode (1) ......................................................... 2-54 2.4.19 Setting method for event counter mode (2) ......................................................... 2-55 2.4.20 Example of peripheral circuit .................................................................................. 2-56 2.4.21 Method of measuring water flow rate ................................................................... 2-56 2.4.22 Example of control procedure ................................................................................ 2-57 2.4.23 Setting method for pulse width measurement mode (1) .................................... 2-58 2.4.24 Setting method for pulse width measurement mode (2) .................................... 2-59 2.4.25 Connection of timer and setting of division ratio ................................................ 2-60 2.4.26 Example of control procedure ................................................................................ 2-61 2.5.1 Memory map of registers relevant to timer Y and timer Z .................................. 2-63 2.5.2 Structure of Port P0 direction register .................................................................... 2-64 2.5.3 Structure of Port P3 direction register .................................................................... 2-64 2.5.4 Structure of Pull-up control register ........................................................................ 2-65 2.5.5 Structure of Port P1P3 control register .................................................................. 2-65 2.5.6 Structure of Timer Y, Z mode register .................................................................... 2-66 2.5.7 Structure of Prescaler Y, Prescaler Z ..................................................................... 2-66 2.5.8 Structure of Timer Y secondary, Timer Z secondary ........................................... 2-67 2.5.9 Structure of Timer Y primary, Timer Z primary ..................................................... 2-67 2.5.10 Structure of Timer Y, Z waveform output control register ................................. 2-68 2.5.11 Structure of One-shot start register ....................................................................... 2-68 2.5.12 Structure of Timer count source set register ....................................................... 2-69 2.5.13 Structure of Interrupt edge selection register ...................................................... 2-69 2.5.14 Structure of CPU mode register ............................................................................ 2-70 2.5.15 Structure of Interrupt request register 1 ............................................................... 2-71 2.5.16 Structure of Interrupt request register 2 ............................................................... 2-71 2.5.17 Structure of Interrupt control register 1 ................................................................ 2-72 2.5.18 Structure of Interrupt control register 2 ................................................................ 2-72 2.5.19 Setting method for timer mode .............................................................................. 2-74 2.5.20 Example of peripheral circuit .................................................................................. 2-75 vi List of figures 7540 Group Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.5.21 Method of measuring water flow rate ................................................................... 2-75 2.5.22 Example of control procedure ................................................................................ 2-76 2.5.23 Timing diagram of programmable waveform generation mode ......................... 2-79 2.5.24 Setting method for programmable waveform generation mode (1) .................. 2-80 2.5.25 Setting method for programmable waveform generation mode (2) .................. 2-81 2.5.26 Example of waveform output .................................................................................. 2-82 2.5.27 Example of control procedure ................................................................................ 2-83 2.5.28 Timing diagram of programmable one-shot generation mode ........................... 2-85 2.5.29 Setting method for programmable one-shot generation mode (1) .................... 2-86 2.5.30 Setting method for programmable one-shot generation mode (2) .................... 2-87 2.5.31 Setting method for programmable one-shot generation mode (3) .................... 2-88 2.5.32 Example of peripheral circuit .................................................................................. 2-89 2.5.33 Example of operation timing ................................................................................... 2-89 2.5.34 Example of control procedure ................................................................................ 2-90 2.5.35 Timing diagram of programmable wait one-shot generation mode ................... 2-93 2.5.36 Setting method for programmable wait one-shot generation mode (1) ............ 2-94 2.5.37 Setting method for programmable wait one-shot generation mode (2) ............ 2-95 2.5.38 Setting method for programmable wait one-shot generation mode (3) ............ 2-96 2.5.39 Example of waveform generation and peripheral circuit .................................... 2-97 2.5.40 Example of control procedure ................................................................................ 2-98 2.6.1 Memory map of registers relevant to serial I/O ................................................... 2-101 2.6.2 Structure of Transmit/Receive buffer register ...................................................... 2-101 2.6.3 Structure of Serial I/O1 status register ................................................................. 2-102 2.6.4 Structure of Serial I/O1 control register ................................................................ 2-102 2.6.5 Structure of UART control register ........................................................................ 2-103 2.6.6 Structure of Baud rate generator ........................................................................... 2-103 2.6.7 Structure of Interrupt request register 1 ............................................................... 2-104 2.6.8 Structure of Interrupt control register 1 ................................................................ 2-104 2.6.9 Serial I/O1 transfer data format ............................................................................. 2-105 2.6.10 Setting method for clock synchronous serial I/O1 (1) ...................................... 2-107 2.6.11 Setting method for clock synchronous serial I/O1 (2) ...................................... 2-108 2.6.12 Connection diagram ............................................................................................... 2-109 2.6.13 Timing chart ............................................................................................................ 2-109 2.6.14 Control procedure of transmitter .......................................................................... 2-110 2.6.15 Control procedure of receiver ............................................................................... 2-111 2.6.16 Setting method for UART of serial I/O1 (1) ....................................................... 2-113 2.6.17 Setting method for UART of serial I/O1 (2) ....................................................... 2-114 2.6.18 Connection diagram ............................................................................................... 2-115 2.6.19 Timing chart ............................................................................................................ 2-115 2.6.20 Control procedure of transmitter .......................................................................... 2-116 2.6.21 Control procedure of receiver ............................................................................... 2-117 2.6.22 Sequence of setting serial I/O1 control register again ..................................... 2-119 2.7.1 Memory map of registers relevant to serial I/O2 ................................................ 2-120 2.7.2 Structure of Port P1 direction register .................................................................. 2-120 2.7.3 Structure of Serial I/O2 control register ................................................................ 2-121 2.7.4 Structure of Serial I/O2 register ............................................................................. 2-121 2.7.5 Structure of Interrupt request register 2 ............................................................... 2-122 2.7.6 Structure of Interrupt control register 2 ................................................................ 2-122 2.7.7 Setting method for serial I/O2 ................................................................................ 2-123 2.7.8 Setting method for serial I/O2 ................................................................................ 2-124 2.7.9 Connection diagram ................................................................................................. 2-125 2.7.10 Timing chart ............................................................................................................ 2-125 vii List of figures 7540 Group Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.7.11 Control procedure of transmission side .............................................................. 2-126 2.7.12 Control procedure of reception side .................................................................... 2-127 2.8.1 Memory map of registers relevant to A/D converter ........................................... 2-129 2.8.2 Structure of A/D control register ............................................................................ 2-129 2.8.3 Structure of A/D conversion register (low-order) ................................................. 2-130 2.8.4 Structure of A/D conversion register (high-order) ............................................... 2-130 2.8.5 Structure of Interrupt request register 2 ............................................................... 2-131 2.8.6 Structure of Interrupt control register 2 ................................................................ 2-131 2.8.7 Relevant registers setting ....................................................................................... 2-132 2.8.8 Connection diagram ................................................................................................. 2-133 2.8.9 Control procedure ..................................................................................................... 2-133 2.8.10 Connection diagram ............................................................................................... 2-134 2.9.1 Memory map of registers relevant to oscillation control .................................... 2-135 2.9.2 Structure of MISRG ................................................................................................. 2-135 2.9.3 Structure of Watchdog timer control register ....................................................... 2-136 2.9.4 Structure of CPU mode register ............................................................................ 2-136 2.9.5 Setting method when the on-chip oscillator is used as the operation clock ... 2-137 2.9.6 Control procedure ..................................................................................................... 2-138 2.9.7 Initial setting method for the oscillation stop detection circuit .......................... 2-140 2.9.8 Setting method for the oscillation stop detection circuit in main processing .. 2-141 2.9.9 State transition .......................................................................................................... 2-142 2.9.10 Example of mode transition .................................................................................. 2-143 2.9.11 Control procedure ................................................................................................... 2-144 CHAPTER 3 APPENDIX 3.1.1 Switching characteristics measurement circuit diagram (General purpose) ....... 3-11 3.1.2 Timing chart (General purpose) ............................................................................... 3-12 3.1.3 Switching characteristics measurement circuit diagram (Extended operating temperature)3-20 3.1.4 Timing chart (Extended operating temperature version) ...................................... 3-21 3.1.5 Switching characteristics measurement circuit diagram (Extended operating temperature 125 C version) ..................................................................................................................... 3-29 Fig. 3.1.6 Timing chart (Extended operating temperature 125 C version) ......................... 3-30 Fig. 3.2.1 VCC-ICC characteristics (in double-speed mode: Mask ROM version) .................. 3-31 Fig. 3.2.2 VCC-ICC characteristics (in high-speed mode: Mask ROM version) ...................... 3-31 Fig. 3.2.3 VCC-ICC characteristics (in middle-speed mode: Mask ROM version) .................. 3-31 Fig. 3.2.4 VCC-ICC characteristics (at WIT instruction execution: Mask ROM version) ........ 3-32 Fig. 3.2.5 VCC-ICC characteristics (at STP instruction execution: Mask ROM version) ....... 3-32 Fig. 3.2.6 VCC-ICC characteristics (addition when operating A/D conversion, f(XIN) = 8 MHz in high-speed mode: Mask ROM version) .............................................................................. 3-33 Fig. 3.2.7 VCC-ICC characteristics (addition when operating A/D conversion, f(XIN) = 6 MHz in double-speed mode: Mask ROM version) ......................................................................... 3-33 Fig. 3.2.8VCC-ICC characteristics (When system is operating by on-chip oscillator, Ceramic oscillation stop: Mask ROM version) .................................................................................................... 3-34 Fig. 3.2.9 VCC-ICC characteristics (When system is operating by on-chip oscillator, at WIT instruction execution, Ceramic oscillation stop: Mask ROM version) ............................................... 3-34 Fig. 3.2.10 f(XIN)-ICC characteristics (in double-speed mode: Mask ROM version) ............. 3-35 Fig. 3.2.11 f(XIN)-ICC characteristics (in high-speed mode: Mask ROM version) ................. 3-35 Fig. 3.2.12 f(XIN)-ICC characteristics (in middle-speed mode: Mask ROM version) ............. 3-35 Fig. 3.2.13 f(XIN)-ICC characteristics (at WIT instruction execution: Mask ROM version) ... 3-36 Fig. 3.2.14 Ta-ICC characteristics (When system is operating by on-chip oscillator, Ceramic oscillation stop: Mask ROM version) .................................................................................. 3-36 Fig. 3.2.15 Ta-ICC characteristics (When system is operating by on-chip oscillator, at WIT instruction execution, Ceramic oscillation stop: Mask ROM version) ............................ 3-36 Fig. Fig. Fig. Fig. Fig. viii List of figures 7540 Group 3.2.16 VCC-VIHL characteristics (I/O port (CMOS): Mask ROM version) ........................ 3-37 3.2.17 VCC-VIHL characteristics (I/O port (TTL): Mask ROM version) ............................ 3-37 3.2.18 VCC-VIHL characteristics (RESET pin: Mask ROM version) ................................. 3-38 3.2.19 VCC-VIHL characteristics (XIN pin: Mask ROM version) ......................................... 3-38 3.2.20 VCC-VIL characteristics (CNVSS pin: Mask ROM version) ..................................... 3-38 3.2.21 VCC-HYS characteristics (RESET pin: Mask ROM version) ................................ 3-39 3.2.22 VCC-HYS characteristics (SIO pin: Mask ROM version) ...................................... 3-39 3.2.23 VCC-HYS characteristics (INT pin: Mask ROM version) ...................................... 3-39 3.2.24 VOH-IOH characteristics of P-channel (VCC = 3.0 V, normal port: Mask ROM version) .. 3-40 3.2.25 VOH-IOH characteristics of P-channel (VCC = 5.0 V, normal port: Mask ROM version) .. 3-40 3.2.26 VOL-IOL characteristics of N-channel (VCC = 3.0 V, normal port: Mask ROM version) ... 3-41 3.2.27 VOL-IOL characteristics of N-channel (VCC = 5.0 V, normal port: Mask ROM version) ... 3-41 3.2.28 VOL-IOL characteristics of N-channel (VCC = 3.0 V, LED drive port: Mask ROM version) ................................................................................................................................................. 3-42 Fig. 3.2.29 VOL-IOL characteristics of N-channel (VCC = 5.0 V, LED drive port: Mask ROM version) ................................................................................................................................................. 3-42 Fig. 3.2.30 VCC-IIL characteristics (Port "L" input current when connecting pull-up transistor: Mask ROM version) .............................................................................................................. 3-43 Fig. 3.2.31 VIN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 8 MHz in high-speed mode: Mask ROM version) ................................................................ 3-44 Fig. 3.2.32 VIN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 6 MHz in double-speed mode: Mask ROM version) ............................................................ 3-44 Fig. 3.2.33 VIN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 4 MHz in double-speed mode: Mask ROM version) ............................................................ 3-44 Fig. 3.2.34 VCC-ROSC characteristics (on-chip oscillator frequency: Mask ROM version) ... 3-45 Fig. 3.2.35 Ta-ROSC characteristics (on-chip oscillator frequency: Mask ROM version) ..... 3-45 Fig. 3.2.36 R-f(XIN) characteristics (RC oscillation frequency: Mask ROM version) ........... 3-46 Fig. 3.2.37 C-f(XIN) characteristics (RC oscillation frequency: Mask ROM version) ........... 3-46 Fig. 3.2.38 VCC-f(XIN) characteristics (RC oscillation frequency: Mask ROM version) ........ 3-47 Fig. 3.2.39 Ta-f(XIN) characteristics (RC oscillation frequency: Mask ROM version) ......... 3-47 Fig. 3.2.40 Definition of A/D conversion aCCuracy ................................................................... 3-48 Fig. 3.2.41 A/D conversion accuracy typical characteristic example-1 (Mask ROM version) .. 3-49 Fig. 3.2.42 A/D conversion accuracy typical characteristic example-2 (Mask ROM version) .. 3-50 Fig. 3.2.43 A/D conversion aCCuracy typical characteristic example-3 (Mask ROM version) .. 3-51 Fig. 3.2.44 VCC-ICC characteristics (in double-speed mode: One Time PROM version) ..... 3-52 Fig. 3.2.45 VCC-ICC characteristics (in high-speed mode: One Time PROM version) ......... 3-52 Fig. 3.2.46 VCC-ICC characteristics (in middle-speed mode: One Time PROM version) ..... 3-52 Fig. 3.2.47 VCC-ICC characteristics (at WIT instruction execution: One Time PROM version) .. 3-53 Fig. 3.2.48 VCC-ICC characteristics (at STP instruction execution: One Time PROM version) .. 3-53 Fig. 3.2.49 VCC-ICC characteristics (addition when operating A/D conversion, f(XIN) = 8 MHz in high-speed mode: One Time PROM version) ................................................................... 3-54 Fig. 3.2.50 VCC-ICC characteristics (addition when operating A/D conversion, f(XIN) = 6 MHz in double-speed mode: One Time PROM version) ............................................................... 3-54 Fig. 3.2.51 VCC-ICC characteristics (When system is operating by on-chip oscillator, Ceramic oscillation stop: One Time PROM version) ....................................................................... 3-55 Fig. 3.2.52 VCC-ICC characteristics (When system is operating by on-chip oscillator, at WIT instruction execution, Ceramic oscillation stop: One Time PROM version) ................. 3-55 Fig. 3.2.53 f(XIN)-ICC characteristics (in double-speed mode: One Time PROM version) .. 3-56 Fig. 3.2.54 f(XIN)-ICC characteristics (in high-speed mode: One Time PROM version) ...... 3-56 Fig. 3.2.55 f(XIN)-ICC characteristics (in middle-speed mode: One Time PROM version) .. 3-56 Fig. 3.2.56 f(XIN)-ICC characteristics (at WIT instruction execution: One Time PROM version) ... 3-57 Fig. 3.2.57 Ta-ICC characteristics (When system is operating by on-chip oscillator, Ceramic oscillation stop: One Time PROM version) ....................................................................... 3-57 Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. ix List of figures 7540 Group Fig. 3.2.58 Ta-ICC characteristics (When system is operating by on-chip oscillator, at WIT instruction execution, Ceramic oscillation stop: One Time PROM version) ................. 3-57 Fig. 3.2.59 VCC-VIHL characteristics (I/O port (CMOS): One Time PROM version) ............. 3-58 Fig. 3.2.60 VCC-VIHL characteristics (I/O port (TTL): One Time PROM version) .................. 3-58 Fig. 3.2.61 VCC-VIHL characteristics (RESET pin: One Time PROM version) ....................... 3-59 Fig. 3.2.62 VCC-VIHL characteristics (XIN pin: One Time PROM version) ............................... 3-59 Fig. 3.2.63 VCC-VIL characteristics (CNVSS pin: One Time PROM version) .......................... 3-59 Fig. 3.2.64 VCC-HYS characteristics (RESET pin: One Time PROM version) ..................... 3-60 Fig. 3.2.65 VCC-HYS characteristics (SIO pin: One Time PROM version) ........................... 3-60 Fig. 3.2.66 VCC-HYS characteristics (INT pin: One Time PROM version) ........................... 3-60 Fig. 3.2.67 VOH-IOH characteristics of P-channel (VCC = 3.0 V, normal port: One Time PROM version) ................................................................................................................................... 3-61 Fig. 3.2.68 VOH-IOH characteristics of P-channel (VCC = 5.0 V, normal port: One Time PROM version) ................................................................................................................................... 3-61 Fig. 3.2.69 VOL-IOL characteristics of N-channel (VCC = 3.0 V, normal port: One Time PROM version) ................................................................................................................................... 3-62 Fig. 3.2.70 VOL-IOL characteristics of N-channel (VCC = 5.0 V, normal port: One Time PROM version) ................................................................................................................................... 3-62 Fig. 3.2.71 VOL-IOL characteristics of N-channel (VCC = 3.0 V, LED drive port: One Time PROM version) ................................................................................................................................... 3-63 Fig. 3.2.72 VOL-IOL characteristics of N-channel (VCC = 5.0 V, LED drive port: One Time PROM version) ................................................................................................................................... 3-63 Fig. 3.2.73 VCC-IIL characteristics (Port "L" input current when connecting pull-up transistor: One Time PROM version) .................................................................................................... 3-64 Fig. 3.2.74 VIN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 8 MHz in high-speed mode: One Time PROM version) ..................................................... 3-65 Fig. 3.2.75 VIN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 6 MHz in double-speed mode: One Time PROM version) ................................................. 3-65 Fig. 3.2.76 VIN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 4 MHz in double-speed mode: One Time PROM version) ................................................. 3-65 Fig. 3.2.77 VCC-ROSC characteristics (on-chip oscillator frequency: One Time PROM version) ..... 3-66 Fig. 3.2.78 Ta-ROSC characteristics (on-chip oscillator frequency: One Time PROM version) ...... 3-66 Fig. 3.2.79 R-f(XIN) characteristics (RC oscillation frequency: One Time PROM version) 3-67 Fig. 3.2.80 C-f(XIN) characteristics (RC oscillation frequency: One Time PROM version) 3-67 Fig. 3.2.81 VCC-f(XIN) characteristics (RC oscillation frequency: One Time PROM version) ... 3-68 Fig. 3.2.82 Ta-f(XIN) characteristics (RC oscillation frequency: One Time PROM version)3-68 Fig. 3.2.83 Definition of A/D conversion accuracy .................................................................. 3-69 Fig. 3.2.84 A/D conversion accuracy typical characteristic example-1 (One Time PROM version) .. 3-70 Fig. 3.2.85 A/D conversion accuracy typical characteristic example-2 (One Time PROM version) .. 3-71 Fig. 3.2.86 A/D conversion accuracy typical characteristic example-3 (One Time PROM version) .. 3-72 Fig. 3.3.1 Sequence of setting serial I/O1 control register again ......................................... 3-80 Fig. 3.3.2 Connection diagram ................................................................................................... 3-82 Fig. 3.3.3 State transition ............................................................................................................ 3-84 Fig. 3.3.4 Switching method of CPU mode register ............................................................... 3-85 Fig. 3.3.5 Sequence of switch the detection edge .................................................................. 3-86 Fig. 3.3.6 Sequence of check of interrupt request bit ............................................................ 3-86 Fig. 3.3.7 Structure of interrupt control register 2 .................................................................. 3-87 Fig. 3.3.8 Initialization of processor status register ................................................................ 3-88 Fig. 3.3.9 Sequence of PLP instruction execution .................................................................. 3-88 Fig. 3.3.10 Stack memory contents after PHP instruction execution ................................... 3-88 Fig. 3.3.11 Status flag at decimal calculations ........................................................................ 3-89 Fig. 3.3.12 Programming and testing of One Time PROM version ...................................... 3-90 x List of figures 7540 Group Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.4.1 Selection of packages ............................................................................................... 3-92 3.4.2 Wiring for the RESET pin ......................................................................................... 3-92 3.4.3 Wiring for clock I/O pins ........................................................................................... 3-93 3.4.4 Wiring for CNVSS pin ................................................................................................ 3-93 3.4.5 Wiring for the VPP pin of the One Time PROM ..................................................... 3-94 3.4.6 Bypass capacitor across the VSS line and the VCC line ........................................ 3-94 3.4.7 Analog signal line and a resistor and a capacitor ................................................ 3-95 3.4.8 Wiring for a large current signal line ...................................................................... 3-95 3.4.9 Wiring of signal lines where potential levels change frequently ......................... 3-96 3.4.10 VSS pattern on the underside of an oscillator ...................................................... 3-96 3.4.11 Setup for I/O ports ................................................................................................... 3-96 3.4.12 Watchdog timer by software ................................................................................... 3-97 3.5.1 Structure of Port Pi (i = 0, 2, 3) .............................................................................. 3-98 3.5.2 Structure of Port P1 ................................................................................................... 3-98 3.5.3 Structure of Port Pi direction register (i = 0, 2, 3) ............................................... 3-99 3.5.4 Structure of Port P1 direction register .................................................................... 3-99 3.5.5 Structure of Pull-up control register ...................................................................... 3-100 3.5.6 Structure of Port P1P3 control register ................................................................ 3-100 3.5.7 Structure of Transmit/Receive buffer register ...................................................... 3-101 3.5.8 Structure of Serial I/O1 status register ................................................................. 3-101 3.5.9 Structure of Serial I/O1 control register ................................................................ 3-102 3.5.10 Structure of UART control register ...................................................................... 3-102 3.5.11 Structure of Baud rate generator ......................................................................... 3-103 3.5.12 Structure of Timer A mode register .................................................................... 3-104 3.5.13 Structure of Timer A register ............................................................................... 3-105 3.5.14 Structure of Timer Y, Z mode register ............................................................... 3-105 3.5.15 Structure of Prescaler Y, Prescaler Z ................................................................. 3-106 3.5.16 Structure of Timer Y secondary, Timer Z secondary ....................................... 3-106 3.5.17 Structure of Timer Y primary, Timer Z primary ................................................. 3-107 3.5.18 Structure of Timer Y, Z waveform output control register ............................... 3-107 3.5.19 Structure of Prescaler 1 ........................................................................................ 3-108 3.5.20 Structure of Timer 1 .............................................................................................. 3-108 3.5.21 Structure of One-shot start register ..................................................................... 3-109 3.5.22 Structure of Timer X mode register .................................................................... 3-110 3.5.23 Structure of Prescaler X ....................................................................................... 3-111 3.5.24 Structure of Timer X .............................................................................................. 3-111 3.5.25 Structure of Timer count source set register ..................................................... 3-112 3.5.26 Structure of Serial I/O2 control register .............................................................. 3-113 3.5.27 Structure of Serial I/O2 register ........................................................................... 3-113 3.5.28 Structure of A/D control register .......................................................................... 3-114 3.5.29 Structure of A/D conversion register (low-order) ............................................... 3-114 3.5.30 Structure of A/D conversion register (high-order) ............................................. 3-115 3.5.31 Structure of MISRG ............................................................................................... 3-115 3.5.32 Structure of Watchdog timer control register ..................................................... 3-116 3.5.33 Structure of Interrupt edge selection register .................................................... 3-116 3.5.34 Structure of CPU mode register .......................................................................... 3-117 3.5.35 Structure of Interrupt request register 1 ............................................................. 3-118 3.5.36 Structure of Interrupt request register 2 ............................................................. 3-118 3.5.37 Structure of Interrupt control register 1 .............................................................. 3-119 3.5.38 Structure of Interrupt control register 2 .............................................................. 3-119 xi List of figures 7540 Group Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.10.1 3.10.2 3.10.3 3.10.4 3.11.1 3.11.2 3.11.3 32P6U-A package pin configuration .................................................................... 3-135 36P2R-A package pin configuration .................................................................... 3-136 32P4B package pin configuration ........................................................................ 3-137 42S1M package pin configuration ........................................................................ 3-138 Memory map of 7540 Group and 7531 Group .................................................. 3-140 Memory map of interrupt vector area of 7540 Group and 7531 Group ........ 3-141 Timer function of 7540 Group and 7531 Group ................................................ 3-142 xii List of tables 7540 Group List of tables CHAPTER 1 HARDWARE Table Table Table Table Table Table Table Table Table 1 2 3 4 5 6 7 8 9 Pin description ................................................................................................................. 1-8 List of supported products ........................................................................................... 1-10 Push and pop instructions of accumulator or processor status register ............... 1-12 Set and clear instructions of each bit of processor status register ....................... 1-13 I/O port function table ................................................................................................... 1-18 Interrupt vector address and priority .......................................................................... 1-21 Special programming adapter ...................................................................................... 1-53 Interrupt sources, vector addresses and interrupt priority ....................................... 1-54 Change of A/D conversion register during A/D conversion ..................................... 1-56 CHAPTER 2 APPLICATION Table Table Table Table 2.1.1 2.2.1 2.4.1 2.6.1 Handling of unused pins ........................................................................................ 2-10 CNTR1 active edge switch bit function ................................................................ 2-15 CNTR0 active edge switch bit function ................................................................ 2-42 Setting example of baud rate generator (BRG) and transfer bit rate values .. 2-112 CHAPTER 3 APPENDIX Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 3.1.1 Absolute maximum ratings ....................................................................................... 3-2 3.1.2 Recommended operating conditions (1) ................................................................ 3-3 3.1.3 Recommended operating conditions (2) ................................................................ 3-4 3.1.4 Electrical characteristics (1) ..................................................................................... 3-5 3.1.5 Electrical characteristics (2) ..................................................................................... 3-6 3.1.6 A/D Converter characteristics .................................................................................. 3-7 3.1.7 Timing requirements (1) ........................................................................................... 3-8 3.1.8 Timing requirements (2) ........................................................................................... 3-8 3.1.9 Timing requirements (3) ........................................................................................... 3-9 3.1.10 Switching characteristics (1) ................................................................................ 3-10 3.1.11 Switching characteristics (2) ................................................................................ 3-10 3.1.12 Switching characteristics (3) ................................................................................ 3-11 3.1.13 Absolute maximum ratings ................................................................................... 3-13 3.1.14 Recommended operating conditions (1) ............................................................ 3-14 3.1.15 Recommended operating conditions (2) ............................................................ 3-15 3.1.16 Electrical characteristics (1) ................................................................................ 3-16 3.1.17 Electrical characteristics (2) ................................................................................ 3-17 3.1.18 A/D Converter characteristics .............................................................................. 3-18 3.1.19 Timing requirements (1) ....................................................................................... 3-19 3.1.20 Timing requirements (2) ....................................................................................... 3-19 3.1.21 Switching characteristics (1) ................................................................................ 3-20 3.1.22 Switching characteristics (2) ................................................................................ 3-20 3.1.23 Absolute maximum ratings ................................................................................... 3-22 3.1.24 Recommended operating conditions (1) ............................................................ 3-23 3.1.25 Recommended operating conditions (2) ............................................................ 3-24 3.1.26 Electrical characteristics (1) ................................................................................ 3-25 3.1.27 Electrical characteristics (2) ................................................................................ 3-26 xiii List of tables 7540 Group Table Table Table Table Table Table Table Table Table Table 3.1.28 A/D Converter characteristics .............................................................................. 3-27 3.1.29 Timing requirements (1) ....................................................................................... 3-28 3.1.30 Timing requirements (2) ....................................................................................... 3-28 3.1.31 Switching characteristics (1) ................................................................................ 3-29 3.1.32 Switching characteristics (2) ................................................................................ 3-29 3.3.1 Programming adapters ........................................................................................... 3-91 3.3.2 PROM programmer address setting ..................................................................... 3-91 3.5.1 CNTR1 active edge switch bit function .............................................................. 3-104 3.5.2 CNTR0 active edge switch bit function .............................................................. 3-110 3.11.1 Differences between 7540 Group and 7531 Group ....................................... 3-139 xiv CHAPTER 1 HARDWARE DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION FUNCTIONAL BLOCK PIN DESCRIPTION GROUP EXPANSION FUNCTIONAL DESCRIPTION NOTES ON PROGRAMMING NOTES ON USE DATA REQUIRED FOR MASK ORDERS ROM PROGRAMMING METHOD FUNCTIONAL DESCRIPTION SUPPLEMENT HARDWARE 7540 Group DESCRIPTION/FEATURES/APPLICATION DESCRIPTION The 7540 Group is the 8-bit microcomputer based on the 740 family core technology. The 7540 Group has a serial I/O, 8-bit timers, a 16-bit timer, and an A/D converter, and is useful for control of home electric appliances and office automation equipment. APPLICATION Office automation equipment, factory automation equipment, home electric appliances, consumer electronics, car, etc. Notes 1: Serial I/O2 can be used in the following cases; (1) Serial I/O1 is not used, (2) Serial I/O1 is used as UART and BRG output divided by 16 is selected as the synchronized clock. 2: In this version, the operating temperature range and total time are limited as follows; 55 C to 85 C: within total 6000 hours, 85 C to 125 C: within total 1000 hours. FEATURES * * * * * * * * * * * * * * Basic machine-language instructions ...................................... 71 The minimum instruction execution time ......................... 0.34 s (at 6 MHz oscillation frequency, double-speed mode for the shortest instruction) Memory size ROM ............................................ 8 K to 32 K bytes RAM ............................................. 384 to 768 bytes Programmable I/O ports ....................... 29 (25 in 32-pin version) Interrupts ................................................. 15 sources, 15 vectors ................................. (14 sources, 14 vectors for 32-pin version) Timers ............................................................................. 8-bit 4 ...................................................................................... 16-bit 1 Serial I/O1 ................... 8-bit 1 (UART or Clock-synchronized) Serial I/O2 (Note 1) ..................... 8-bit 1 (Clock-synchronized) A/D converter ............................................... 10-bit 8 channels .................................................... (6 channels for 32-pin version) Clock generating circuit ............................................. Built-in type (low-power dissipation by an on-chip oscillator enabled) (connect to external ceramic resonator or quartz-crystal oscillator permitting RC oscillation) Watchdog timer ............................................................ 16-bit 1 Power source voltage XIN oscillation frequency at ceramic oscillation, in double-speed mode At 6 MHz .................................................................... 4.5 to 5.5 V XIN oscillation frequency at ceramic oscillation, in high-speed mode At 8 MHz .................................................................... 4.0 to 5.5 V At 4 MHz .................................................................... 2.4 to 5.5 V At 2 MHz .................................................................... 2.2 to 5.5 V XIN oscillation frequency at RC oscillation in high-speed mode or middle-speed mode At 4 MHz .................................................................... 4.0 to 5.5 V At 2 MHz .................................................................... 2.4 to 5.5 V At 1 MHz .................................................................... 2.2 to 5.5 V Power dissipation Mask ROM version ....................................... 22.5 mW (standard) One Time PROM version ................................ 30 mW (standard) Operating temperature range ................................... -20 to 85 C (-40 to 85 C for extended operating temperature version) (-40 to 125 C for extended operating temperature 125 C version (Note 2)) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-2 HARDWARE 7540 Group PIN CONFIGURATION PIN CONFIGURATION (TOP VIEW) P06 P05 P04 P03/TXOUT P02/TZOUT P01/TYOUT P00/CNTR1 P37/INT0 23 20 24 22 21 19 18 P07 P10/RXD1 P11/TXD1 P12/SCLK1/SCLK2 P13/SRDY1/SDATA2 P14/CNTR0 P20/AN0 P21/AN1 17 25 26 27 28 29 30 31 32 M37540Mx-XXXGP M37540MxT-XXXGP M37540MxV-XXXGP M37540ExGP M37540E8T-XXXGP M37540E8V-XXXGP 16 15 14 13 12 11 10 9 P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0) VSS XOUT XIN 2 3 4 5 6 7 Package type: 32P6U-A Fig. 1 Pin configuration (32P6U-A type) P12/SCLK1/SCLK2 P13/SRDY1/SDATA2 P14/CNTR0 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 VREF RESET CNVSS Vcc XIN XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 P22/AN2 P23/AN3 P24/AN4 P25/AN5 VREF RESET CNVSS VCC 1 8 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 P11/TXD1 P10/RXD1 P07 P06 P05 P04 P03/TXOUT P02/TZOUT P01/TYOUT P00/CNTR1 P37/INT0 P36(LED6)/INT1 P35(LED5) P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0) Package type: 36P2R-A Fig. 2 Pin configuration (36P2R-A type) M37540Mx-XXXFP M37540MxT-XXXFP M37540MxV-XXXFP M37540E8FP M37540E8T-XXXFP M37540E8V-XXXFP Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-3 HARDWARE 7540 Group PIN CONFIGURATION P12/SCLK1/SCLK2 P13/SRDY1/SDATA2 P14/CNTR0 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 VREF RESET CNVSS VCC XIN XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P11/TXD1 P10/RXD1 P07 P06 P05 P04 P03/TXOUT P02/TZOUT P01/TYOUT P00/CNTR1 P37/INT0 P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0) Package type: 32P4B M37540Mx-XXXSP M37540ExSP Fig. 3 Pin configuration (32P4B-A type) P14/CNTR0 NC NC P20/AN0 P21/AN1 NC P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 NC NC VREF RESET CNVSS Vcc XIN XOUT VSS 1 2 3 4 5 6 7 42 41 40 39 38 37 36 8 9 10 11 12 13 14 15 16 17 18 19 20 21 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P13/SRDY1/SDATA2 P12/SCLK1/SCLK2 P11/TXD1 P10/RXD1 P07 P06 P05 P04 P03/TXOUT P02/TZOUT P01/TYOUT P00/CNTR1 NC P37/INT0 P36(LED6)/INT1 P35(LED5) P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0) Outline 42S1M Fig. 4 Pin configuration (42S1M type) M37540RSS Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-4 7540 Group FUNCTIONAL BLOCK DIAGRAM (Package: 32P6U) Clock input Clock output Reset input VSS 11 8 6 7 X IN X OU VCC CNVSS RESET 5 4 3 2 1 32 31 17 16 15 14 13 12 30 29 28 27 26 25 24 23 22 21 20 19 18 VREF I/O port P3 I/O port P2 I/O port P1 I/O port P0 Key-on wakeup Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z FUNCTIONAL BLOCK 9 T 10 Clock generating circuit CPU RAM X Prescaler X (8) CNTR0 ROM Y Prescaler Y (8) S PC H PS PCL Prescaler Z (8) TXOUT A Prescaler 1 (8) Timer X (8) Fig. 5 Functional block diagram (32P6U package) Timer 1 (8) Timer Y (8) TYOUT Timer Z (8) TZOUT Watchdog timer INT0 Reset Timer A (16) CNTR1 0 A/D converter (10) SI/O1(8) SI/O2(8) INT0 P3(6) P2(6) P1(5) P0(8) FUNCTIONAL BLOCK HARDWARE 1-5 7540 Group FUNCTIONAL BLOCK DIAGRAM (Package: 36P2R) Clock input Clock output X IN X OUT VSS CNVSS 14 18 15 13 VCC Reset input RESET 12 26 25 24 23 22 21 20 19 11 10 9 8 7 6 5 4 3 2 1 36 35 34 33 32 31 30 29 28 27 VREF HARDWARE I/O port P3 I/O port P2 I/O port P1 I/O port P0 Key-on wakeup Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z CPU 16 17 Clock generating circuit RAM X Y Prescaler Y (8) S PCH PS PCL Prescaler Z (8) CNTR0 ROM Prescaler X (8) A Prescaler 1 (8) Timer 1 (8) Timer X (8) TXOUT Fig. 6 Functional block diagram (36P2R package) Timer Y (8) TYOUT Timer Z (8) TZOUT Watchdog timer INT0 Reset Timer A (16) CNTR1 0 A/D converter (10) SI/O1(8) SI/O2(8) INT0 INT1 P3(8) P2(8) P1(5) P0(8) FUNCTIONAL BLOCK 1-6 7540 Group FUNCTIONAL BLOCK DIAGRAM (Package: 32P4B) Clock input X IN VSS VCC CNVSS 12 13 11 16 Clock output X OUT Reset input RESET 10 22 21 20 19 18 17 987654 3 2 1 32 31 30 29 28 27 26 25 24 23 VREF I/O port P3 I/O port P2 I/O port P1 I/O port P0 Key-on wakeup Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z CPU Prescaler 1 (8) A X CNTR0 14 15 Clock generating circuit Timer 1 (8) Timer X (8) TXOUT RAM Prescaler X (8) Prescaler Y (8) Prescaler Z (8) Timer A (16) CNTR1 INT0 0 Fig. 7 Functional block diagram (32P4B package) ROM Y S PCH PS PCL Timer Y (8) TYOUT Timer Z (8) TZOUT Watchdog timer Reset A/D converter (10) SI/O1(8) SI/O2(8) INT0 P3(6) P2(6) P1(5) P0(8) FUNCTIONAL BLOCK HARDWARE 1-7 HARDWARE 7540 Group PIN DESCRIPTION PIN DESCRIPTION Table 1 Pin description Pin Name Vcc, Vss Power source (Note 1) VREF Analog reference voltage CNVss CNVss RESET Reset input XIN Clock input Function *Apply voltage of 2.2 to 5.5 V to Vcc, and 0 V to Vss. *Reference voltage input pin for A/D converter *Chip operating mode control pin, which is always connected to Vss. *Reset input pin for active "L" *Input and output pins for main clock generating circuit *Connect a ceramic resonator or quartz crystal oscillator between the XIN and XOUT pins. *For using RC oscillator, short between the XIN and XOUT pins, and connect the capacitor and resistor. *If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. * When the on-chip oscillator is selected as the main clock, connect XIN pin to VSS and leave XOUT open. * Key-input (key-on wake up *8-bit I/O port. interrupt input) pins *I/O direction register allows each pin to be individually pro* Timer Y, timer Z, timer X and grammed as either input or output. timer A function pin *CMOS compatible input level *CMOS 3-state output structure *Whether a built-in pull-up resistor is to be used or not can be determined by program. *5-bit I/O port *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level *CMOS 3-state output structure *CMOS/TTL level can be switched for P10, P12 and P13 Function expect a port function XOUT Clock output P00/CNTR1 P01/TYOUT P02/TZOUT P03/TXOUT P04-P07 I/O port P0 P10/RxD1 I/O port P1 P11/TxD1 P12/SCLK1/SCLK2 P13/SRDY1/SDATA2 P14/CNTR0 P20/AN0-P27/AN7 I/O port P2 (Note 2) P30-P35 I/O port P3 (Note 3) * Serial I/O1 function pin * Serial I/O1 function pin * Serial I/O2 function pin * Timer X function pin *8-bit I/O port having almost the same function as P0 * Input pins for A/D converter *CMOS compatible input level *CMOS 3-state output structure *8-bit I/O port *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level (CMOS/TTL level can be switched for P36 and P37). *CMOS 3-state output structure *P30 to P36 can output a large current for driving LED. *Whether a built-in pull-up resistor is to be used or not can be determined by program. * Interrupt input pins P36/INT1 P37/INT0 Notes 1: VCC = 2.4 to 5.5 V for the extended operating temperature version and the extended operating temperature 125 C version. 2: P26/AN6 and P27/AN7 do not exist for the 32-pin version, so that Port P2 is a 6-bit I/O port. 3: P35 and P36/INT1 do not exist for the 32-pin version, so that Port P3 is a 6-bit I/O port. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-8 HARDWARE 7540 Group GROUP EXPANSION GROUP EXPANSION We plan to expand the 7540 group as follow: Memory type Support for Mask ROM version, One Time PROM version, and Emulator MCU . Memory size ROM/PROM size ................................................. 8 K to 32 K bytes RAM size .............................................................. 384 to 768 bytes Package 32P4B .................................................. 32-pin plastic molded SDIP 32P6U-A ...................... 0.8 mm-pitch 32-pin plastic molded LQFP 36P2R-A ...................... 0.8 mm-pitch 36-pin plastic molded SSOP 42S1M .................................... 42-pin shrink ceramic PIGGY BACK ROM size (bytes) M37540E8V M37540E8T M37540E8 32K M37540M4V 16K M37540M4T M37540M4 M37540E2 M37540M2V 8K M37540M2T M37540M2 0 384 512 768 RAM size (bytes) Fig. 8 Memory expansion plan Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-9 HARDWARE 7540 Group GROUP EXPANSION Currently supported products are listed below. Table 2 List of supported products (P) ROM size (bytes) RAM size Part Number (bytes) ROM size for User () 384 8192 M37540M2-XXXSP (8062) M37540M2-XXXFP M37540M2T-XXXFP M37540M2V-XXXFP M37540M2-XXXGP M37540M2T-XXXGP M37540M2V-XXXGP M37540M4-XXXSP M37540M4-XXXFP M37540M4T-XXXFP M37540M4V-XXXFP M37540M4-XXXGP M37540M4T-XXXGP M37540M4V-XXXGP M37540E2SP M37540E2FP M37540E2GP M37540E8SP M37540E8FP M37540E8T-XXXFP M37540E8V-XXXFP M37540E8GP M37540E8T-XXXGP M37540E8V-XXXGP M37540RSS 768 Package Remarks 16384 (16254) 512 8192 (8062) 32768 (32638) 384 768 32P4B Mask ROM version 36P2R-A Mask ROM version Mask ROM version (extended operating temperature version) Mask ROM version (extended operating temperature 125 C version) 32P6U-A Mask ROM version Mask ROM version (extended operating temperature version) Mask ROM version (extended operating temperature 125 C version) 32P4B Mask ROM version 36P2R-A Mask ROM version Mask ROM version (extended operating temperature version) Mask ROM version (extended operating temperature 125 C version) 32P6U-A Mask ROM version Mask ROM version (extended operating temperature version) Mask ROM version (extended operating temperature 125 C version) 32P4B One Time PROM version (blank) 36P2R-A One Time PROM version (blank) 32P6U-A One Time PROM version (blank) 32P4B One Time PROM version (blank) 36P2R-A One Time PROM version (blank) One Time PROM version (shipped after programming, extended operating temperature version) One Time PROM version (shipped after programming, extended operating temperature 125 C version) 32P6U-A One Time PROM version (blank) One Time PROM version (shipped after programming, extended operating temperature version) One Time PROM version (shipped after programming, extended operating temperature 125 C version) 42S1M Emulator MCU Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-10 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The MCU uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine-language instructions or the SERIES 740 Stack pointer (S) The stack pointer is an 8-bit register used during subroutine calls and interrupts. The stack is used to store the current address data and processor status when branching to subroutines or interrupt routines. The lower eight bits of the stack address are determined by the contents of the stack pointer. The upper eight bits of the stack address are determined by the Stack Page Selection Bit. If the Stack Page Selection Bit is "0", then the RAM in the zero page is used as the stack area. If the Stack Page Selection Bit is "1", then RAM in page 1 is used as the stack area. The Stack Page Selection Bit is located in the SFR area in the zero page. Note that the initial value of the Stack Page Selection Bit varies with each microcomputer type. Also some microcomputer types have no Stack Page Selection Bit and the upper eight bits of the stack address are fixed. The operations of pushing register contents onto the stack and popping them from the stack are shown in Fig. 10. Accumulator (A) The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. Index register X (X), Index register Y (Y) Both index register X and index register Y are 8-bit registers. In the index addressing modes, the value of the OPERAND is added to the contents of register X or register Y and specifies the real address. When the T flag in the processor status register is set to "1", the value contained in index register X becomes the address for the second OPERAND. Program counter (PC) The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. b7 b0 A b7 b0 Accumulator Index Register X b0 X b7 Y b7 b0 Index Register Y Stack Pointer b0 S b15 b7 PCH b7 PCL b0 Program Counter N V T B D I Z C Processor Status Register (PS) Carry Flag Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index X Mode Flag Overflow Flag Negative Flag Fig. 9 740 Family CPU register structure Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-11 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION On-going Routine Interrupt request (Note) Execute JSR M (S) Store Return Address on Stack (S) M (S) (S) (PCH) (S - 1) (PCL) (S - 1) M (S) (S) M (S) (S) M (S) (S) (PCH) (S - 1) (PCL) (S - 1) (PS) (S - 1) Store Contents of Processor Status Register on Stack Store Return Address on Stack Subroutine Execute RTS Restore Return Address (S) (PCL) (S) (PCH) (S + 1) M (S) (S + 1) M (S) Interrupt Service Routine Execute RTI (S) (PS) (S) (PCL) (S) (PCH) (S + 1) M (S) (S + 1) M (S) (S + 1) M (S) I Flag "0" to "1" Fetch the Jump Vector Restore Contents of Processor Status Register Restore Return Address Note : The condition to enable the interrupt Interrupt enable bit is "1" Interrupt disable flag is "0" Fig. 10 Register push and pop at interrupt generation and subroutine call Table 3 Push and pop instructions of accumulator or processor status register Accumulator Processor status register Push instruction to stack PHA PHP Pop instruction from stack PLA PLP Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-12 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION Processor status register (PS) The processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic operation. Branch operations can be performed by testing the Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. After reset, the Interrupt disable (I) flag is set to "1", but all other flags are undefined. Since the Index X mode (T) and Decimal mode (D) flags directly affect arithmetic operations, they should be initialized in the beginning of a program. (1) Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. (2) Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is "0", and cleared if the result is anything other than "0". (3) Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is "1". When an interrupt occurs, this flag is automatically set to "1" to prevent other interrupts from interfering until the current interrupt is serviced. (4) Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is "0"; decimal arithmetic is executed when it is "1". Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. (5) Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always "0". When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to "1". The saved processor status is the only place where the break flag is ever set. (6) Index X mode flag (T) When the T flag is "0", arithmetic operations are performed between accumulator and memory, e.g. the results of an operation between two memory locations is stored in the accumulator. When the T flag is "1", direct arithmetic operations and direct data transfers are enabled between memory locations, i.e. between memory and memory, memory and I/O, and I/O and I/O. In this case, the result of an arithmetic operation performed on data in memory location 1 and memory location 2 is stored in memory location 1. The address of memory location 1 is specified by index register X, and the address of memory location 2 is specified by normal addressing modes. (7) Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. (8) Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 4 Set and clear instructions of each bit of processor status register Set instruction Clear instruction C flag SEC CLC Z flag - - I flag SEI CLI D flag SED CLD B flag - - T flag SET CLT V flag - CLV N flag - - Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-13 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION [CPU mode register] CPUM The CPU mode register contains the stack page selection bit. This register is allocated at address 003B16. Switching method of CPU mode register Switch the CPU mode register (CPUM) at the head of program after releasing Reset in the following method. b7 b0 CPU mode register (CPUM: address 003B16, initial value: 8016) Processor mode bits (Note 1) b1 b0 0 0 Single-chip mode 01 10 Not available 11 Stack page selection bit 0 : 0 page 1 : 1 page On-chip oscillator oscillation control bit 0 : On-chip oscillator oscillation enabled 1 : On-chip oscillator oscillation stop XIN oscillation control bit 0 : Ceramic or RC oscillation enabled 1 : Ceramic or RC oscillation stop Oscillation mode selection bit (Note 1) 0 : Ceramic oscillation 1 : RC oscillation Clock division ratio selection bits b7 b6 0 0 : f() = f(XIN)/2 (High-speed mode) 0 1 : f() = f(XIN)/8 (Middle-speed mode) 1 0 : applied from on-chip oscillator 1 1 : f() = f(XIN) (Double-speed mode)(Note 2) Note 1: The bit can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. However, by reset the bit is initialized and can be rewritten, again. (It is not disable to write any data to the bit for emulator MCU "M37540RSS".) 2: These bits are used only when a ceramic oscillation is selected. Do not use these when an RC oscillation is selected. Fig. 11 Structure of CPU mode register After releasing reset Start with an on-chip oscillator Switch the oscillation mode selection bit (bit 5 of CPUM) An initial value is set as a ceramic oscillation mode. When it is switched to an RC oscillation, its oscillation starts. Wait by on-chip oscillator operation until establishment of oscillator clock When using a ceramic oscillation, wait until establlishment of oscillation from oscillation starts. When using an RC oscillation, wait time is not required basically (time to execute the instruction to switch from an on-chip oscillator meets the requirement). Select 1/1, 1/2, 1/8 or on-chip oscillator. Switch the clock division ratio selection bits (bits 6 and 7 of CPUM) Main routine Fig. 12 Switching method of CPU mode register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-14 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION Memory Special function register (SFR) area The SFR area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for a stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is a user area for storing programs. Interrupt vector area The interrupt vector area contains reset and interrupt vectors. Zero page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special page The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. 000016 SFR area 004016 010016 Zero page RAM RAM area RAM capacity (bytes) address XXXX16 XXXX16 Reserved area 044016 Not used YYYY16 Reserved ROM area (128 bytes) 384 512 768 01BF16 023F16 033F16 ZZZZ16 ROM ROM area ROM capacity (bytes) address YYYY16 address ZZZZ16 FF0016 8192 16384 32768 E00016 C00016 800016 E08016 C08016 808016 FFDC16 Interrupt vector area FFFE16 FFFF16 Reserved ROM area Special page Fig. 13 Memory map diagram Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-15 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 Timer Y, Z mode register (TYZM) Prescaler Y (PREY) Timer Y secondary (TYS) Timer Y primary (TYP) Timer Y, Z waveform output control register (PUM) Prescaler Z (PREZ) Timer Z secondary (TZS) Timer Z primary (TZP) Prescaler 1 (PRE1) Timer 1 (T1) One-shot start register (ONS) Timer X mode register (TXM) Prescaler X (PREX) Timer X (TX) Timer count source set register (TCSS) Serial I/O2 control register (SIO2CON) Serial I/O2 register (SIO2) A/D control register (ADCON) A/D conversion register (low-order) (ADL) A/D conversion register (high-order) (ADH) Pull-up control register (PULL) Port P1P3 control register (P1P3C) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) Timer A mode register (TAM) Timer A (low-order) (TAL) Timer A (high-order) (TAH) 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 MISRG Watchdog timer control register (WDTCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Note : Do not access to the SFR area including nothing. Fig. 14 Memory map of special function register (SFR) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-16 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION I/O Ports [Direction registers] PiD The I/O ports have direction registers which determine the input/ output direction of each pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input or output. When "1" is set to the bit corresponding to a pin, this pin becomes an output port. When "0" is set to the bit, the pin becomes an input port. When data is read from a pin set to output, not the value of the pin itself but the value of port latch is read. Pins set to input are floating, and permit reading pin values. If a pin set to input is written to, only the port latch is written to and the pin remains floating. [Pull-up control register] PULL By setting the pull-up control register (address 001616), ports P0 and P3 can exert pull-up control by program. However, pins set to output are disconnected from this control and cannot exert pull-up control. Note: P26/AN6, P27/AN7, P35 and P36 do not exist for the 32-pin version. Accordingly, the following settings are required; * Set direction registers of ports P26 and P27 to output. * Set direction registers of ports P35 and P36 to output. [Port P1P3 control register] P1P3C By setting the port P1P3 control register (address 001716), a CMOS input level or a TTL input level can be selected for ports P10, P12, P13, P36, and P37 by program. b7 b0 Pull-up control register (PULL: address 001616, initial value: 0016) P00 pull-up control bit P01 pull-up control bit P02, P03 pull-up control bit P04 - P07 pull-up control bit P30 - P33 pull-up control bit P34 pull-up control bit P35, P36 pull-up control bit P37 pull-up control bit Note: Pins set to output ports are disconnected from pull-up control. Fig. 15 Structure of pull-up control register 0 : Pull-up Off 1 : Pull-up On b7 b0 Port P1P3 control register (P1P3C: address 0017 16, initial value: 00 16) P37/INT0 input level selection bit 0 : CMOS level 1 : TTL level P36/INT1 input level selection bit 0 : CMOS level 1 : TTL level P10,P12,P13 input level selection bit 0 : CMOS level 1 : TTL level Not used Note: Keep setting the P3 6/INT1 input level selection bit to "0" (initial value) for 32-pin version. Fig. 16 Structure of port P1P3 control register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-17 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION Table 5 I/O port function table Pin P00/CNTR1 P01/TYOUT P02/TZOUT P03/TXOUT P04-P07 Name Input/output I/O format I/O port P0 I/O individual *CMOS compatible bits input level *CMOS 3-state output (Note 1) Non-port function Key input interrupt Timer X function output Timer Y function output Timer Z function output Timer A function input Diagram No. Related SFRs (1) Pull-up control register (2) Timer Y mode register (3) Timer Z mode register (4) Timer X mode register Timer Y,Z waveform output control register Timer A mode register (5) Serial I/O1 control register (6) (7) Serial I/O1 control register (8) Serial I/O2 control register (9) Timer X mode register (10) A/D control register (11) (12) P10/RxD1 P11/TxD1 P12/SCLK1/SCLK2 P13/SRDY1/SDATA2 P14/CNTR0 P20/AN0- P27/AN7 P30-P35 P36/INT1 P37/INT0 I/O port P1 I/O port P2 (Note 2) I/O port P3 (Note 3) Serial I/O1 function input/output Serial I/O2 function input/output Timer X function input/output A/D conversion input External interrupt input Interrupt edge selection register Notes 1: Ports P10, P12, P13, P36, and P37 are CMOS/TTL level. 2: P26/AN6 and P27/AN7 do not exist for the 32-pin version. 3: P35 and P36/INT1 do not exist for the 32-pin version. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-18 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION (1)Port P00 Pull-up control Direction register (2)Ports P01, P02 Pull-up control Direction register Data bus Port latch Data bus Port latch CNTR1 interrupt input To key input interrupt generating circuit ** Programmable waveform generation mode Timer output To key input interrupt generating circuit P00 key-on wakeup selection bit (3)Port P03 Pull-up control Direction register (4)Ports P04-P07 Pull-up control Direction register Data bus Port latch Timer output P03/TXOUT output valid Data bus Port latch To key input interrupt generating circuit To key input interrupt generating circuit (5)Port P10 Serial I/O1 enable bit Receive enable bit Direction register Data bus Port latch P10, P12, P13 input level selection bit (6)Port P11 P11/TxD1 P-channel output disable bit Serial I/O1 enable bit Transmit enable bit Direction register Data bus Port latch Serial I/O1 input * (7)Port P12 Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit Serial I/O1 output SCLK2 pin selection bit Serial I/O1 mode selection bit Serial I/O1 enable bit Direction register Data bus Port latch P10, P12, P13 input level selection bit Serial I/O1, serial I/O2 clock output Serial I/O1, serial I/O2 clock input * * ** P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register. When the TTL level is selected, there is no hysteresis characteristics. P02/TZOUT; Programmable waveform generation mode Programmable one-shot generation mode Programmable wait one-shot generation mode Fig. 17 Block diagram of ports (1) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-19 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION (8) Port P13 (9) Port P14 SDATA2 output in operation signal SDATA2 pin selection bit Serial I/O mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register Data bus Direction register Port latch Data bus Port latch Pulse output mode Timer output CNTR0 interrupt input P10, P12, P13 input level selection bit Serial I/O1 ready output Serial I/O2 output Serial I/O2 input * (10) Ports P20-P27 Direction register (11) Ports P30-P35 Pull-up control Direction register Data bus Port latch Data bus Port latch A/D converter input Analog input pin selection bit (12) Ports P36, P37 Pull-up control Direction register Data bus Port latch P3 input level selection bit INT interrupt input * * P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register. When the TTL level is selected, there is no hysteresis characteristics. Fig. 18 Block diagram of ports (2) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-20 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION Interrupts Interrupts occur by 15 different sources : 5 external sources, 9 internal sources and 1 software source. Interrupt control All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit, and they are controlled by the interrupt disable flag. When the interrupt enable bit and the interrupt request bit are set to "1" and the interrupt disable flag is set to "0", an interrupt is accepted. The interrupt request bit can be cleared by program but not be set. The interrupt enable bit can be set and cleared by program. The reset and BRK instruction interrupt can never be disabled with any flag or bit. All interrupts except these are disabled when the interrupt disable flag is set. When several interrupts occur at the same time, the interrupts are received according to priority. Interrupt operation Upon acceptance of an interrupt the following operations are automatically performed: 1. The processing being executed is stopped. 2. The contents of the program counter and processor status register are automatically pushed onto the stack. 3. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 4. Concurrently with the push operation, the interrupt destination address is read from the vector table into the program counter. Table 6 Interrupt vector address and priority Interrupt source Priority Reset (Note 2) Serial I/O1 receive Serial I/O1 transmit INT0 INT1 (Note 3) Key-on wake-up CNTR0 CNTR1 Timer X Timer Y Timer Z Timer A Serial I/O2 A/D conversion Timer 1 Reserved area BRK instruction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Vector addresses (Note 1) High-order FFFD16 FFFB16 FFF916 FFF716 FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDF16 FFDD16 Low-order FFFC16 FFFA16 FFF816 FFF616 FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDE16 FFDC16 s Notes on use When setting the followings, the interrupt request bit may be set to "1". *When switching external interrupt active edge Related register: Interrupt edge selection register (address 003A16) Timer X mode register (address 2B16) Timer A mode register (address 1D16) When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. Set the corresponding interrupt enable bit to "0" (disabled). Set the interrupt edge select bit (active edge switch bit). Set the corresponding interrupt request bit to "0" after 1 or more instructions have been executed. Set the corresponding interrupt enable bit to "1" (enabled). Interrupt request generating conditions At reset input At completion of serial I/O1 data receive At completion of serial I/O1 transmit shift or when transmit buffer is empty At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At falling of conjunction of input logical level for port P0 (at input) At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At timer X underflow At timer Y underflow At timer Z underflow At timer A underflow At completion of transmit/receive shift At completion of A/D conversion At timer 1 underflow Not available At BRK instruction execution Remarks Non-maskable Valid only when serial I/O1 is selected Valid only when serial I/O1 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (valid at falling) External interrupt (active edge selectable) External interrupt (active edge selectable) STP release timer underflow Non-maskable software interrupt Note 1: Vector addressed contain internal jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 3: It is an interrupt which can use only for 36 pin version. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-21 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION Interrupt request bit Interrupt enable bit Interrupt disable flag I BRK instruction Reset Interrupt request Fig. 19 Interrupt control b7 b0 Interrupt edge selection register (INTEDGE : address 003A16, initial value : 0016) INT0 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active INT1 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active Not used (returns "0" when read) P00 key-on wakeup enable bit 0 : Key-on wakeup enabled 1 : Key-on wakeup disabled b7 b0 Interrupt request register 1 (IREQ1 : address 003C16, initial value : 0016) Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit INT0 interrupt request bit INT1 interrupt request bit Key-on wake up interrupt request bit CNTR0 interrupt request bit CNTR1 interrupt request bit Timer X interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt request register 2 (IREQ2 : address 003D16, initial value : 0016) Timer Y interrupt request bit Timer Z interrupt request bit Timer A interrupt request bit Serial I/O2 interrupt request bit A/D conversion interrupt request bit Timer 1 interrupt request bit Not used (returns "0" when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 1 (ICON1 : address 003E16, initial value : 0016) Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit INT0 interrupt enable bit INT1 interrupt enable bit (Do not write "1" to this bit for 32-pin version) Key-on wake up interrupt enable bit CNTR0 interrupt enable bit CNTR1 interrupt enable bit Timer X interrupt enable bit 0 : Interrupts disabled 1 : Interrupts enabled b7 b0 Interrupt control register 2 (ICON2 : address 003F16, initial value : 0016) Timer Y interrupt enable bit Timer Z interrupt enable bit Timer A interrupt enable bit Serial I/O2 interrupt enable bit A/D conversion interrupt enable bit Timer 1 interrupt enable bit Not used (returns "0" when read) (Do not write "1" to this bit) 0 : Interrupts disabled 1 : Interrupts enabled Fig. 20 Structure of Interrupt-related registers Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-22 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION Key Input Interrupt (Key-On Wake-Up) A key-on wake-up interrupt request is generated by applying "L" level to any pin of port P0 that has been set to input mode. In other words, it is generated when the AND of input level goes from "1" to "0". An example of using a key input interrupt is shown in Figure 21, where an interrupt request is generated by pressing one of the keys provided as an active-low key matrix which uses ports P00 to P03 as input ports. Port PXx "L" level output PULL register bit 3 = "0" * P07 output ** Port P07 latch Falling edge detection Port P07 Direction register = "1" Key input interrupt request PULL register bit 3 = "0" * P06 output ** Port P06 latch Port P06 Direction register = "1" Falling edge detection PULL register bit 3 = "0" * P05 output ** Port P05 latch Port P05 Direction register = "1" Falling edge detection PULL register bit 3 = "0" * P04 output ** Port P04 latch Port P04 Direction register = "1" Falling edge detection PULL register bit 2 = "1" * P03 input ** Port P03 latch Port P03 Direction register = "0" Falling edge detection Port P0 Input read circuit PULL register bit 2 = "1" * P02 input ** Port P02 latch Port P02 Direction register = "0" Falling edge detection PULL register bit 1 = "1" * P01 input ** Port P01 latch Port P01 Direction register = "0" Falling edge detection PULL register bit 0 = "1" * P00 input Port P00 key-on wakeup selection bit ** Port P00 latch Port P00 Direction register = "0" Falling edge detection * P-channel transistor for pull-up ** CMOS output buffer Fig. 21 Connection example when using key input interrupt and port P0 block diagram Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-23 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION Timers The 7540 Group has 5 timers: timer 1, timer A, timer X, timer Y and timer Z. The division ratio of every timer and prescaler is 1/(n+1) provided that the value of the timer latch or prescaler is n. All the timers are down count timers. When a timer reaches "0", an underflow occurs at the next count pulse, and the corresponding timer latch is reloaded into the timer. When a timer underflows, the interrupt request bit corresponding to each timer is set to "1". qTimer A Timer A is a 16-bit timer and counts the signal which is the oscillation frequency divided by 16. When Timer A underflows, the timer A interrupt request bit is set to "1". Timer A consists of the low-order of Timer A (TAL) and the high-order of Timer A (TAH). Timer A has the timer A latch to retain the reload value. The value of timer A latch is set to Timer A at the timing shown below. * When Timer A undeflows. * When an active edge is input from CNTR1 pin (valid only when period measurement mode and pulse width HL continuously measurement mode). When writing to both the low-order of Timer A (TAL) and the highorder of Timer A (TAH) is executed, the value is written to both the timer A latch and Timer A. When reading from the low-order of Timer A (TAL) and the high-order of Timer A (TAH) is executed, the following values are read out according to the operating mode. * In timer mode, event counter mode: The count value of Timer A is read out. * In period measurement mode, pulse width HL continuously measurement mode: The measured value is read out. Be sure to write to/read out the low-order of Timer A (TAL) and the high-order of Timer A (TAH) in the following order; Read Read the high-order of Timer A (TAH) first, and the low-order of Timer A (TAL) next and be sure to read out both TAH and TAL. Write Write to the low-order of Timer A (TAL) first, and the high-order of Timer A (TAH) next and be sure to write to both TAL and TAH. Timer A can be selected in one of 4 operating modes by setting the timer A mode register. (1) Timer mode Timer A counts the oscillation frequency divided by 16. Each time the count clock is input, the contents of Timer A is decremented by 1. When the contents of Timer A reach "000016", an underflow occurs at the next count clock, and the timer A latch is reloaded into Timer A. The division ratio of Timer A is 1/(n+1) provided that the value of Timer A is n. (2) Period measurement mode In the period measurement mode, the pulse period input from the P00/CNTR1 pin is measured. CNTR1 interrupt request is generated at rising/falling edge of CNTR1 pin input singal. Simultaneousuly, the value in the timer A latch is reloaded inTimer A and count continues. The active edge of CNTR1 pin input signal can be selected from rising or falling by the CNTR1 active edge switch bit .The count value when trigger input from CNTR1 pin is accepted is retained until Timer A is read once. qTimer 1 Timer 1 is an 8-bit timer and counts the prescaler output. When Timer 1 underflows, the timer 1 interrupt request bit is set to "1". Prescaler 1 is an 8-bit prescaler and counts the signal which is the oscillation frequency divided by 16. Prescaler 1 and Timer 1 have the prescaler 1 latch and the timer 1 latch to retain the reload value, respectively. The value of prescaler 1 latch is set to Prescaler 1 when Prescaler 1 underflows.The value of timer 1 latch is set to Timer 1 when Timer 1 underflows. When writing to Prescaler 1 (PRE1) is executed, the value is written to both the prescaler 1 latch and Prescaler 1. When writing to Timer 1 (T1) is executed, the value is written to both the timer 1 latch and Timer 1. When reading from Prescaler 1 (PRE1) and Timer 1 (T1) is executed, each count value is read out. Timer 1 always operates in the timer mode. Prescaler 1 counts the signal which is the oscillation frequency divided by 16. Each time the count clock is input, the contents of Prescaler 1 is decremented by 1. When the contents of Prescaler 1 reach "0016", an underflow occurs at the next count clock, and the prescaler 1 latch is reloaded into Prescaler 1 and count continues. The division ratio of Prescaler 1 is 1/(n+1) provided that the value of Prescaler 1 is n. The contents of Timer 1 is decremented by 1 each time the underflow signal of Prescaler 1 is input. When the contents of Timer 1 reach "0016", an underflow occurs at the next count clock, and the timer 1 latch is reloaded into Timer 1 and count continues. The division ratio of Timer 1 is 1/(m+1) provided that the value of Timer 1 is m. Accordingly, the division ratio of Prescaler 1 and Timer 1 is 1/((n+1)(m+1)) provided that the value of Prescaler 1 is n and the value of Timer 1 is m. Timer 1 cannot stop counting by software. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-24 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION (3) Event counter mode Timer A counts signals input from the P00/CNTR1 pin. Except for this, the operation in event counter mode is the same as in timer mode. The active edge of CNTR1 pin input signal can be selected from rising or falling by the CNTR1 active edge switch bit . (4) Pulse width HL continuously measurement mode In the pulse width HL continuously measurement mode, the pulse width ("H" and "L" levels) input to the P00/CNTR1 pin is measured. CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. The count value when trigger input from the CNTR1 pin is accepted is retained until Timer A is read once. Timer A can stop counting by setting "1" to the timer A count stop bit in any mode. Also, when Timer A underflows, the timer A interrupt request bit is set to "1". Note on Timer A is described below; s Note on Timer A CNTR1 interrupt active edge selection CNTR1 interrupt active edge depends on the CNTR1 active edge switch bit. When this bit is "0", the CNTR1 interrupt request bit is set to "1" at the falling edge of the CNTR1 pin input signal. When this bit is "1", the CNTR1 interrupt request bit is set to "1" at the rising edge of the CNTR1 pin input signal. However, in the pulse width HL continuously measurement mode, CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR1 active edge switch bit. qTimer X Timer X is an 8-bit timer and counts the prescaler X output. When Timer X underflows, the timer X interrupt request bit is set to "1". Prescaler X is an 8-bit prescaler and counts the signal selected by the timer X count source selection bit. Prescaler X and Timer X have the prescaler X latch and the timer X latch to retain the reload value, respectively. The value of prescaler X latch is set to Prescaler X when Prescaler X underflows.The value of timer X latch is set to Timer X when Timer X underflows. When writing to Prescaler X (PREX) is executed, the value is written to both the prescaler X latch and Prescaler X. When writing to Timer X (TX) is executed, the value is written to both the timer X latch and Timer X. When reading from Prescaler X (PREX) and Timer X (TX) is executed, each count value is read out. Timer X can can be selected in one of 4 operating modes by setting the timer X operating mode bits of the timer X mode register. (1) Timer mode Prescaler X counts the count source selected by the timer X count source selection bits. Each time the count clock is input, the contents of Prescaler X is decremented by 1. When the contents of Prescaler X reach "0016", an underflow occurs at the next count clock, and the prescaler X latch is reloaded into Prescaler X and count continues. The division ratio of Prescaler X is 1/(n+1) provided that the value of Prescaler X is n. The contents of Timer X is decremented by 1 each time the underflow signal of Prescaler X is input. When the contents of Timer X reach "0016", an underflow occurs at the next count clock, and the timer X latch is reloaded into Timer X and count continues. The division ratio of Timer X is 1/(m+1) provided that the value of Timer X is m. Accordingly, the division ratio of Prescaler X and Timer X is 1/((n+1)(m+1)) provided that the value of Prescaler X is n and the value of Timer X is m. (2) Pulse output mode In the pulse output mode, the waveform whose polarity is inverted each time timer X underflows is output from the CNTR0 pin. The output level of CNTR0 pin can be selected by the CNTR0 active edge switch bit. When the CNTR0 active edge switch bit is "0", the output of CNTR0 pin is started at "H" level. When this bit is "1", the output is started at "L" level. Also, the inverted waveform of pulse output from CNTR0 pin can be output from TXOUT pin by setting "1" to the P03/TXOUT output valid bit. When using a timer in this mode, set the port P14 and P03 direction registers to output mode. (3) Event counter mode The timer A counts signals input from the P14/CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. The active edge of CNTR0 pin input signal can be selected from rising or falling by the CNTR0 active edge switch bit . b7 b0 Timer A mode register (TAM : address 001D16, initial value: 0016) Not used (return "0" when read) Timer A operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode CNTR1 active edge switch bit 0 : Count at rising edge in event counter mode Measure the falling edge period in period measurement mode Falling edge active for CNTR1 interrupt 1 : Count at falling edge in event counter mode Measure the rising edge period in period measurement mode Rising edge active for CNTR1 interrupt Timer A count stop bit 0 : Count start 1 : Count stop Fig. 22 Structure of timer A mode register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-25 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION (4) Pulse width measurement mode In the pulse width measurement mode, the pulse width of the signal input to P14/CNTR0 pin is measured. The operation of Timer X can be controlled by the level of the signal input from the CNTR0 pin. When the CNTR0 active edge switch bit is "0", the signal selected by the timer X count source selection bit is counted while the input signal level of CNTR0 pin is "H". The count is stopped while the pin is "L". Also, when the CNTR0 active edge switch bit is "1", the signal selected by the timer X count source selection bit is counted while the input signal level of CNTR0 pin is "L". The count is stopped while the pin is "H". Timer X can stop counting by setting "1" to the timer X count stop bit in any mode. Also, when Timer X underflows, the timer X interrupt request bit is set to "1". Note on Timer X is described below; s Note on Timer X CNTR0 interrupt active edge selection CNTR0 interrupt active edge depends on the CNTR0 active edge switch bit. When this bit is "0", the CNTR0 interrupt request bit is set to "1" at the falling edge of CNTR0 pin input signal. When this bit is "1", the CNTR0 interrupt request bit is set to "1" at the rising edge of CNTR0 pin input signal. b7 b0 Timer X mode register (TXM : address 002B16, initial value: 0016) Timer X operating mode bits b1 b0 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR0 active edge switch bit 0 : Interrupt at falling edge Count at rising edge (in event counter mode) 1 : Interrupt at rising edge Count at falling edge (in event counter mode) Timer X count stop bit 0 : Count start 1 : Count stop P03/TXOUT output valid bit 0 : Output invalid (I/O port) 1 : Output valid (Inverted CNTR 0 output) Not used (return "0" when read) Fig. 23 Structure of timer X mode register b7 b0 Timer count source set register (TCSS : address 002E16, initial value: 0016) Timer X count source selection bits b1 b0 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : f(XIN) (Note 1) 1 1 : Not available Timer Y count source selection bits b3 b2 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : On-chip oscillator output (Note 2) 1 1 : Not available Timer Z count source selection bits b5 b4 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : Timer Y underflow 1 1 : Not available Fix this bit to "0". Not used (return "0" when read) Notes 1: f(XIN) can be used as timer X count source when using a ceramic resonator or on-chip oscillator. Do not use it at RC oscillation. 2: System operates using an on-chip oscillator as a count Source by setting the on-chip oscillator to oscillation enabled by bit 3 of CPUM. Fig. 24 Timer count source set register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-26 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION qTimer Y Timer Y is an 8-bit timer and counts the prescaler Y output. When Timer Y underflows, the timer Y interrupt request bit is set to "1". Prescaler Y is an 8-bit prescaler and counts the signal selected by the timer Y count source selection bit. Prescaler Y has the prescaler Y latch to retain the reload value. Timer Y has the timer Y primary latch and timer Y secondary latch to retain the reload value. The value of prescaler Y latch is set to Prescaler Y when Prescaler Y underflows.The value of timer Y primary latch or timer Y secondary latch are set to Timer Y when Timer Y underflows. As for the value to transfer to Timer Y, either of timer Y primary or timer Y secondary is selected depending on the timer Y operating mode. When writing to Prescaler Y (PREY), timer Y primary (TYP) or timer Y secondary (TYS) is executed, writing to "latch only" or "latch and prescaler (timer)" can be selected by the setting value of the timer Y write control bit. Be sure to set the timer Y write control bit because there are some notes according to the operating mode. When reading from Prescaler Y (PREY) is executed, the count value of Prescaler Y is read out. When reading from timer Y primary (TYP) is executed, the count value of Timer Y is read out. The count value of Timer Y can be read out by reading from the timer Y primary (TYP) even when the value of timer Y primary latch or timer Y secondary latch is counted. When reading the timer Y secondary (TYS) is executed, the undefined value is read out. Timer Y can be selected in one of 2 operating modes by setting the timer Y operating mode bits of the timer Y, Z mode register. (1) Timer mode Prescaler Y counts the count source selected by the timer Y count source selection bits. Each time the count clock is input, the contents of Prescaler Y is decremented by 1. When the contents of Prescaler Y reach "0016", an underflow occurs at the next count clock, and the prescaler Y latch is reloaded into Prescaler Y. The division ratio of Prescaler Y is 1/(n+1) provided that the value of Prescaler Y is n. The contents of Timer Y is decremented by 1 each time the underflow signal of Prescaler Y is input. When the contents of Timer Y reach "0016", an underflow occurs at the next count clock, and the timer Y primary latch is reloaded into Timer Y and count continues. (In the timer mode, the contents of timer Y primary latch is counted. Timer Y secondary latch is not used in this mode.) The division ratio of Timer Y is 1/(m+1) provided that the value of Timer Y is m. Accordingly, the division ratio of Prescaler Y and Timer Y is 1/((n+1)(m+1)) provided that the value of Prescaler Y is n and the value of Timer Y is m. In the timer mode, writing to "latch only" or "latches and Prescaler Y and timer Y primary" can be selected by the setting value of the timer Y write control bit. (2) Programmable waveform generation mode In the programmable waveform generation mode, timer counts the setting value of timer Y primary and the setting value of timer Y secondary alternately, the waveform inverted each time Timer Y underflows is output from TYOUT pin. When using this mode, be sure to set "1" to the timer Y write control bit to select "write to latch only". Also, set the port P01 direction registers to output mode. The active edge of output waveform is set by the timer Y output level latch (b5) of the timer Y, Z waveform output control register (PUM). When "0" is set to b5 of PUM, "H" interval by the setting value of TYP or "L" interval by the setting value of TYS is output alternately. When "1" is set to b5 of PUM, "L" interval by the setting value of TYP or "H" interval by the setting value of TYS is output alternately. Also, in this mode, the primary interval and the secondary interval of the output waveform can be extended respectively for 0.5 cycle of timer count source clock by setting the timer Y primary waveform extension control bit (b2) and the timer Y secondary waveform extension control bit (b3) of PUM to "1". As a result, the waveforms of more accurate resolution can be output. When b2 and b3 of PUM are used, the frequency and duty of the output waveform are as follows; Waveform frequency: FYOUT= 2TMYCL 2(TYP+1)+2(TYS+1)+(EXPYP+EXPYS) Duty: DYOUT= 2(TYP+1)+EXPYP (2(TYP+1)+EXPYP)+(2(TYS+1)+EXPYS) TMYCL: Timer Y count source (frequency) TYP: Timer Y primary (8bit) TYS: Timer Y secondary (8bit) EXPYP: Timer Y primary waveform extension control bit (1bit) EXPYS: Timer Y secondary waveform extension control bit (1bit) In the programmable waveform generation mode, when values of the TYP, TYS, EXPYP and EXPYS are changed, the output waveform is changed at the beginning (timer Y primary waveform interval) of waveform period. When the count values are changed, set values to the TYS, EXPYP and EXPYS first. After then, set the value to TYP. The values are set all at once at the beginning of the next waveform period when the value is set to TYP. (When writing at timer stop is executed, writing to TYP at last is required.) Notes on programmable waveform generation mode is described below; Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-27 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION s Notes on programmable generation waveform mode * Count set value In the programmable waveform generation mode, values of TYS, EXPYP, and EXPYS are valid by writing to TYP because the setting to them is executed all at once by writing to TYP. Even when changing TYP is not required, write the same value again. * Write timing to TYP In the programmable waveform generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TYP and the timing of timer underflow during the secondary interval simultanesously. * Usage of waveform extension function The waveform extension function by the timer Y waveform extension control bit can be used only when "0016" is set to Prescaler Y. When the value other than "0016" is set to Prescaler Y, be sure to set "0" to EXPYP and EXPYS. * Timer Y write mode When using this mode, be sure to set "1" to the timer Y write control bit to select "write to latch only". Timer Y can stop counting by setting "1" to the timer Y count stop bit in any mode. Also, when Timer Y underflows, the timer Y interrupt request bit is set to "1". Timer Y reloads the value of latch when counting is stopped by the timer Y count stop bit. (When timer is read out while timer is stopped, the value of latch is read. The value of timer can be read out only while timer is operating.) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-28 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION qTimer Z Timer Z is an 8-bit timer and counts the prescaler Z output. When Timer Z underflows, the timer Z interrupt request bit is set to "1". Prescaler Z is an 8-bit prescaler and counts the signal selected by the timer Z count source selection bit. Prescaler Z has the prescaler Z latch to retain the reload value. Timer Z has the timer Z primary latch and timer Z secondary latch to retain the reload value. The value of prescaler Z latch is set to Prescaler Z when Prescaler Z underflows.The value of timer Z primary latch or timer Z secondary latch are set to Timer Z when Timer Z underflows. As for the value to transfer to Timer Z, either of timer Z primary or timer Z secondary is selected depending on the timer Z operating mode. When writing to Prescaler Z (PREZ), timer Z primary (TZP) or timer Z secondary (TZS) is executed, writing to "latch only" or "latches and Prescaler Z and Timer Z" can be selected by the setting value of the timer Z write control bit. Be sure to set the write control bit because there are some notes according to the operating mode. When reading from Prescaler Z (PREZ) is executed, the count value of Prescaler Z is read out. When reading from timer Z primary (TZP) is executed, the count value of Timer Z is read out. The count value of Timer Z can be read out by reading from the timer Z primary (TZP) even when the value of timer Z primary latch or timer Z secondary latch is counted. When reading the timer Z secondary (TZS) is executed, the undefined value is read out. Timer Z can be selected in one of 4 operating modes by setting the timer Z operating mode bits of the timer Y, Z mode register. (1) Timer mode Prescaler Z counts the count source selected by the timer Z count source selection bits. Each time the count clock is input, the contents of Prescaler Z is decremented by 1. When the contents of Prescaler Z reach "0016", an underflow occurs at the next count clock, and the prescaler Z latch is reloaded into Prescaler Z. The division ratio of Prescaler Z is 1/(n+1) provided that the value of Prescaler Z is n. The contents of Timer Z is decremented by 1 each time the underflow signal of Prescaler Z is input. When the contents of Timer Z reach "0016", an underflow occurs at the next count clock, and the timer Z primary latch is reloaded into Timer Z and count continues. (In the timer mode, the contents of timer Z primary latch is counted. Timer Z secondary latch is not used in this mode.) The division ratio of Timer Z is 1/(m+1) provided that the value of Timer Z is m. Accordingly, the division ratio of Prescaler Z and Timer Z is 1/((n+1)(m+1)) provided that the value of Prescaler Z is n and the value of Timer Z is m. In the timer mode, writing to "latch only" or "latches and Prescaler Z and timer Z primary" can be selected by the setting value of the timer Z write control bit. (2) Programmable waveform generation mode In the programmable waveform generation mode, timer counts the setting value of timer Z primary and the setting value of timer Z secondary alternately, the waveform inverted each time Timer Z underflows is output from TZOUT pin. When using this mode, be sure to set "1" to the timer Z write control bit to select "write to latch only". Also, set the port P02 direction registers to output mode. The active edge of output waveform is set by the timer Z output level latch (b4) of the timer Y, Z waveform output control register (PUM). When "0" is set to b4 of PUM, "H" interval by the setting value of TZP or "L" interval by the setting value of TZS is output alternately. When "1" is set to b4 of PUM, "L" interval by the setting value of TZP or "H" interval by the setting value of TZS is output alternately. Also, in this mode, the primary interval and the secondary interval of the output waveform can be extended respectively for 0.5 cycle of timer count source clock by setting the timer Z primary waveform extension control bit (b0) and the timer Z secondary waveform extension control bit (b1) of PUM to "1". As a result, the waveforms of more accurate resolution can be output. When b0 and b1 of PUM are used, the frequency and duty of the output waveform are as follows; Waveform frequency: FZOUT= 2TMZCL 2(TZP+1)+2(TZS+1)+(EXPZP+EXPZS) Duty: DZOUT= 2(TZP+1)+EXPZP (2(TZP+1)+EXPZP)+(2(TZS+1)+EXPZS TMZCL: Timer Z count source (frequency) TZP: Timer Z primary (8bit) TZS: Timer Z secondary (8bit) EXPZP: Timer Z primary waveform extension control bit (1bit) EXPZS: Timer Z secondary waveform extension control bit (1bit) In the programmable waveform generation mode, when values of the TZP, TZS, EXPZP and EXPZS are changed, the output waveform is changed at the beginning (timer Z primary waveform interval) of waveform period. When the count values are changed, set values to the TZS, EXPZP and EXPZS first. After then, set the value to TZP. The values are set all at once at the beginning of the next waveform period when the value is set to TZP. (When writing at timer stop is executed, writing to TZP at last is required.) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-29 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION Notes on the programmable waveform generation mode are described below; s Notes on programmable waveform generation mode * Count set value In the programmable waveform generation mode, values of TZS, EXPZP, and EXPZS are valid by writing to TZP because the setting to them is executed all at once by writing to TZP. Even when changing TZP is not required, write the same value again. * Write timing to TZP In the programmable waveform generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow during the secondary interval simultanesously. * Usage of waveform extension function The waveform extension function by the timer Z waveform extension control bit can be used only when "0016" is set to Prescaler Z. When the value other than "0016" is set to Prescaler Z, be sure to set "0" to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the count source, the waveform extension function cannot be used. * Timer Z write mode When using this mode, be sure to set "1" to the timer Z write control bit to select "write to latch only". (3) Programmable one-shot generation mode In the programmable one-shot generation mode, the one-shot pulse by the setting value of timer Z primary can be output from TZOUT pin by software or external trigger. When using this mode, be sure to set "1" to the timer Z write control bit to select "write to latch only". Also, set the port P02 direction registers to output mode. In this mode, TZS is not used. The active edge of output waveform is set by the timer Z output level latch (b5) of the timer Y, Z waveform output control register (PUM). When "0" is set to b5 of PUM, "H" pulse during the interval of the TZP setting value is output. When "1" is set to b5 of PUM, "L" pulse during the interval of the TZP setting value is output. Also, in this mode, the interval of the one-shot pulse output can be extended for 0.5 cycle of timer count source clock by setting the timer Z primary waveform extension control bit (b2) of PUM to "1". As a result, the waveforms of more accurate resolution can be output. In the programmable one-shot generation mode, the trigger by software or the external INT0 pin can be accepted by writing "0" to the timer Z count stop bit after the count value is set. (At the time when "0" is written to the timer Z count stop bit, Timer Z stops.) By writing "1" to the timer Z one-shot start bit, or by inputting the valid trigger to the INT0 pin after the trigger to the INT0 pin becomes valid by writing "1" to the INT0 pin one-shot trigger control bit, Timer Z starts counting, at the same time, the output of TZOUT pin is inverted. When Timer Z underflows, the output of TZOUT pin is inverted again and Timer Z stops. When also the trigger of INT0 pin is accepted, the contents of the one-shot start bit is changed to "1" by hardware. The falling or rising can be selected as the edge of the valid trigger of INT0 pin by the INT0 pin one-shot trigger edge selection bit. During the one-shot pulse output interval, the one-shot pulse output can be stopped forcibly by writing "0" to the timer Z one-shot start bit. In the programmable one-shot generation mode, when the count values are changed, set value to the EXPZP first. After then, set the value to TZP. The values are set all at once at the beginning of the next one-shot pulse when the value is set to TZP. (When writing at timer stop is executed, writing to TZP at last is required.) Notes on the programmable one-shot generation mode are described below; s Notes on programmable one-shot generation mode * Count set value In the programmable one-shot generation mode, the value of EXPZP becomes valid by writing to TZP. Even when changing TZP is not required, write the same value again. * Write timing to TZP In the programmable one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow simultanesously. * Usage of waveform extension function The waveform extension function by the timer Z waveform extension control bit can be used only when "0016" is set to Prescaler Z. When the value other than "0016" is set to Prescaler Z, be sure to set "0" to EXPZP. Also, when the timer Y underflow is selected as the count source, the waveform extension function cannot be used. * Timer Z write mode When using this mode, be sure to set "1" to the timer Z write control bit to select "write to latch only". Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-30 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION (4) Programmable wait one-shot generation mode In the programmable wait one-shot generation mode, the one-shot pulse by the setting value of timer Z secondary can be output from TZOUT pin by software or external trigger to INT0 pin after the wait by the setting value of the timer Z primary. When using this mode, be sure to set "1" to the timer Z write control bit to select "write to latch only". Also, set the port P02 direction registers to output mode. The active edge of output waveform is set by the timer Z output level latch (b5) of the timer Y, Z waveform output control register (PUM). When "0" is set to b5 of PUM, after the wait during the interval of the TZP setting value, "H" pulse during the interval of the TZS setting value is output. When "1" is set to b5 of PUM, after the wait during the interval of the TZP setting value, "L" pulse during the interval of the TZS setting value is output. Also, in this mode, the intervals of the wait and the one-shot pulse output can be extended for 0.5 cycle of timer count source clock by setting EXPZP and EXPZS of PUM to "1". As a result, the waveforms of more accurate resolution can be output. In the programmable one-shot generation mode, the trigger by software or the external INT0 pin can be accepted by writing "0" to the timer Z count stop bit after the count value is set. (At the time when "0" is written to the timer Z count stop bit, Timer Z stops.) By writing "1" to the timer Z one-shot start bit, or by inputting the valid trigger to the INT0 pin after the trigger to the INT0 pin becomes valid by writing "1" to the INT0 pin one-shot trigger control bit, Timer Z starts counting. While Timer Z counts the TZP, the initial value of the TZOUT pin output is retained. When Timer Z underflows, the value of TZS is reloaded, at the same time, the output of TZOUT pin is inverted. When Timer Z underflows, the output of TZOUT pin is inverted again and Timer Z stops. When also the trigger of INT0 pin is accepted, the contents of the one-shot start bit is changed to "1" by hardware. The falling or rising can be selected as the edge of the valid trigger of INT0 pin by the INT0 pin one-shot trigger edge selection bit. During the wait interval and the one-shot pulse output interval, the one-shot pulse output can be stopped forcibly by writing "0" to the timer Z one-shot start bit. In the programmable wait one-shot generation mode, when the count values are changed, set values to the TZS, EXPZP and EXPZS first. After then, set the value to TZP. The values are set all at once at the beginning of the next wait interval when the value is set to TZP. (When writing at timer stop is executed, writing to TZP at last is required.) Notes on the programmable wait one-shot generation mode are described below; s Notes on programmable wait one-shot generation mode * Count set value In the programmable wait one-shot generation mode, values of TZS, EXPZP and EXPZS are valid by writing to TZP. Even when changing TZP is not required, write the same value again. * Write timing to TZP In the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow during the secondary interval simultanesously. * Usage of waveform extension function The waveform extension function by the timer Z waveform extension control bit can be used only when "0016" is set to Prescaler Z. When the value other than "0016" is set to Prescaler Z, be sure to set "0" to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the count source, the waveform extension function cannot be used. * Timer Z write mode When using this mode, be sure to set "1" to the timer Z write control bit to select "write to latch only". Timer Z can stop counting by setting "1" to the timer Z count stop bit in any mode. Also, when Timer Z underflows, the timer Z interrupt request bit is set to "1". Timer Z reloads the value of latch when counting is stopped by the timer Z count stop bit. (When timer is read out while timer is stopped, the value of latch is read. The value of timer can be read out only while timer is operating.) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-31 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION b7 b0 Timer Y, Z mode register (TYZM : address 002016, initial value: 0016) Timer Y operating mode bit 0 : Timer mode 1 : Programmable waveform generation mode Not used (return "0" when read) Timer Y write control bit 0 : Write to latch and timer simultaneously 1 : Write to only latch Timer Y count stop bit 0 : Count start 1 : Count stop Timer Z operating mode bits b5 b4 0 0 : Timer mode 0 1 : Programmable waveform generation mode 1 0 : Programmable one-shot generation mode 1 1 : Programmable wait one-shot generation mode Timer Z write control bit 0 : Write to latch and timer simultaneously 1 : Write to only latch Timer Z count stop bit 0 : Count start 1 : Count stop Fig. 25 Structure of timer Y, Z mode register b7 b0 Timer Y, Z waveform output control register (PUM : address 002416, initial value: 0016) Timer Y primary waveform extension control bit 0 : Waveform not extended 1 : Waveform extended Timer Y secondary waveform extension control bit 0 : Waveform not extended 1 : Waveform extended Timer Z primary waveform extension control bit 0 : Waveform not extended 1 : Waveform extended Timer Z secondary waveform extension control bit 0 : Waveform not extended 1 : Waveform extended Timer Y output level latch 0 : "L" output 1 : "H" output Timer Z output level latch 0 : "L" output 1 : "H" output INT0 pin one-shot trigger control bit 0 : INT0 pin one-shot trigger invalid 1 : INT0 pin one-shot trigger valid INT0 pin one-shot trigger active edge selection bit 0 : Falling edge trigger 1 : Rising edge trigger Fig. 26 Structure of timer Y, Z waveform output control register b7 b0 One-shot start register (ONS : address 002A 16, initial value: 0016) Timer Z one-shot start bit 0 : One-shot stop 1 : One-shot start Not used (return "0" when read) Fig. 27 Structure of one-shot start register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-32 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION Data bus Prescaler 1 latch (8) Timer 1 latch (8) f(XIN)/16 Prescaler 1 (8) Pulse width HL continuously measurement mode Rising edge detected Timer 1 (8) Timer 1 interrupt request bit Period measurement mode Falling edge detected P00/CNTR1 CNTR1 active edge switch bit Data bus Timer A (low-order) latch (8) Timer A (high-order) latch (8) Timer A (low-order) (8) f(XIN)/16 Timer A operation mode bit Timer A count stop bit Timer A (high-order) (8) Timer A interrupt request bit Fig. 28 Block diagram of timer 1 and timer A Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-33 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION Data bus f(XIN)/16 f(XIN)/2 f(XIN) Timer X count source selection bits Prescaler X latch (8) Pulse width Timer mode measurement Pulse output mode mode Prescaler X (8) Timer X latch (8) Timer X (8) P14/CNTR0 CNTR0 active edge switch bit "0" Event counter mode Timer X interrupt request bit Timer X count stop bit CNTR0 interrupt request bit Q Q Toggle flip-flop T R Writing to timer X latch Pulse output mode "1" CNTR0 active "1" edge switch bit Port P14 direction register P03/ TXOUT Port P03 latch Port P14 latch Pulse output mode "0" Data bus P03/TXOUT output valid Port P03 direction register Timer Y count source selection bits f(XIN)/16 f(XIN)/2 On-chip oscillator clock RING (on-chip oscillator output in Fig. 51, 52) Timer Y count stop bit Timer Y primary waveform extension control bit Q P01/TYOUT Port P01 latch Port P01 direction register Q Timer Y output level latch Timer Y secondary waveform extension control bit Toggle flip-flop T Prescaler Y (8) Timer Y (8) Timer Y interrupt request bit Prescaler Y latch (8) Timer Y primary latch (8) Timer Y secondary latch (8) Waveform extension function Programmable waveform gengeration mode Data bus Prescaler Z latch (8) Timer Z count source selection bits f(XIN)/16 f(XIN)/2 Timer Z primary latch (8) Timer Z secondary latch (8) Prescaler Z (8) Timer Z (8) Programmable one-shot generation mode Programmable wait one-shot generation mode Timer Z one-shot start bit Timer Z interrupt request bit Timer Z count stop bit INT0 pin trigger active edge selection bit P37/INT0 One-shot pulse trigger input INT0 interrupt request bit Timer Z primary waveform extenstion control bit Q Toggle flip flop T Timer Z output level latch Waveform extension function P02/TZOUT Port P02 latch Port P02 direction register Programmable waveform generation mode Programmable one-shot generation mode Programmable wait one-shot generation mode Q Timer Z secondary waveform extenstion control bit Fig. 29 Block diagram of timer X, timer Y and timer Z Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-34 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION Serial I/O qSerial I/O1 Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O1 mode can be selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register (bit 6) to "1". For clock synchronous serial I/O1, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB. Data bus Serial I/O1 control register Address 001A16 Address 001816 Receive buffer register P10/RXD1 Receive shift register Shift clock P12/SCLK1 Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit XIN BRG count source selection bit 1/4 Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 1/4 P13/SRDY1 F/F Falling-edge detector Shift clock Clock control circuit Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 P11/TXD1 Transmit shift register Transmit buffer register Address 001816 Data bus Fig. 30 Block diagram of clock synchronous serial I/O1 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD Serial input RxD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Receive enable signal SRDY1 Write pulse to receive/transmit buffer register (address 001816) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection TBE = 1 TSC = 0 Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" . Fig. 31 Operation of clock synchronous serial I/O1 function Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-35 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit of the serial I/O1 control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Data bus Address 001816 Receive buffer register OE Character length selection bit ST detector 7 bits Receive shift register Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 P10/RXD1 8 bits PE FE SP detector Clock control circuit Serial I/O1 synchronous clock selection bit P12/SCLK1 BRG count source selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 1/4 ST/SP/PA generator 1/16 P11/TXD1 Character length selection bit Transmit buffer register Address 001816 Data bus Transmit shift register UART control register Address 001B16 XIN Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Fig. 32 Block diagram of UART serial I/O1 Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 TBE=0 TBE=1 TSC=1 Serial output TXD ST D0 D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) SP ST D0 D1 SP Generated at 2nd bit in 2-stop-bit mode Receive buffer read signal RBF=0 RBF=1 RBF=1 Serial input RXD ST D0 D1 SP ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes "1," can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1." 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Fig. 33 Operation of UART serial I/O1 function Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-36 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION [Transmit buffer register/receive buffer register (TB/RB)] 001816 The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0". [Serial I/O1 status register (SIO1STS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O1 status register are initialized to "0" at reset, but if the transmit enable bit of the serial I/O1 control register has been set to "1", the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1". [Serial I/O1 control register (SIO1CON)] 001A16 The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART control register (UARTCON)] 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P11/TXD1 pin. [Baud rate generator (BRG)] 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. s Notes on serial I/O * Serial I/O interrupt When setting the transmit enable bit to "1", the serial I/O transmit interrupt request bit is automatically set to "1". When not requiring the interrupt occurrence synchronized with the transmission enabled, take the following sequence. Set the serial I/O transmit interrupt enable bit to "0" (disabled). Set the transmit enable bit to "1". Set the serial I/O transmit interrupt request bit to "0" after 1 or more instructions have been executed. Set the serial I/O transmit interrupt enable bit to "1" (enabled). * I/O pin function when serial I/O1 is enabled. The functions of P12 and P13 are switched with the setting values of a serial I/O1 mode selection bit and a serial I/O1 synchronous clock selection bit as follows. (1) Serial I/O1 mode selection bit "1" : Clock synchronous type serial I/O is selected. Setup of a serial I/O1 synchronous clock selection bit "0" : P12 pin turns into an output pin of a synchronous clock. "1" : P12 pin turns into an input pin of a synchronous clock. Setup of a SRDY1 output enable bit (SRDY) "0" : P13 pin can be used as a normal I/O pin. "1" : P13 pin turns into a SRDY output pin. (2) Serial I/O1 mode selection bit "0" : Clock asynchronous (UART) type serial I/O is selected. Setup of a serial I/O1 synchronous clock selection bit "0": P12 pin can be used as a normal I/O pin. "1": P12 pin turns into an input pin of an external clock. When clock asynchronous (UART) type serial I/O is selected, it is P13 pin. It can be used as a normal I/O pin. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-37 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION b7 b0 Serial I/O1 status register (SIO1STS : address 0019 16, initial value: 00 16) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read) b7 b0 Serial I/O1 control register (SIO1CON : address 001A 16, initial value: 00 16) BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P13 pin operates as ordinary I/O pin 1: P13 pin operates as S RDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P10 to P13 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P10 to P13operate as serial I/O pins) b7 b0 UART control register (UARTCON : address 001B 16, initial value: E0 16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P11/TXD1 P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return "1" when read) Fig. 34 Structure of serial I/O1-related registers Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-38 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION qSerial I/O2 The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O2 the transmitter and the receiver must use the same clock. When the internal clock is used, transfer is started by a write signal to the serial I/O2 register. Note: Serial I/O2 can be used in the following cases; (1) Serial I/O1 is not used, (2) Serial I/O1 is used as UART and BRG output divided by 16 is selected as the synchronized clock. [Serial I/O2 control register] SIO2CON The serial I/O2 control register contains 8 bits which control various serial I/O functions. * Set "0" to bit 3 to receive. * At reception, clear bit 7 to "0" by writing a dummy data to the serial I/O2 register after completion of shift. b7 b0 Serial I/O2 control register (SIO2CON: address 003016, initila value: 0016) Internal synchronous clock selection bits 000 : f(XIN)/8 001 : f(XIN)/16 010 : f(XIN)/32 011 : f(XIN)/64 110 : f(XIN)/128 111 : f(XIN)/256 SDATA2 pin selection bit (Note) 0 : I/O port / SDATA2 input 1 : SDATA2 output Not used (returns "0" when read) Transfer direction selection bit 0 : LSB first 1 : MSB first SCLK2 pin selection bit 0 : External clock (SCLK2 is an input) 1 : Internal clock (SCLK2 is an output) Transmit / receive shift completion flag 0 : shift in progress 1 : shift completed Note : When using it as a SDATA input, set the port P13 direction register to "0". Fig. 35 Structure of serial I/O2 control registers Data bus 1/8 1/16 Divider 1/32 1/64 1/128 1/256 XIN SCLK2 pin selection bit "1" "0" Internal synchronous clock selection bits SCLK SCLK2 pin selection bit "0" P12/SCLK2 "1" P12 latch Serial I/O counter 2 (3) Serial I/O2 interrupt request SDATA2 pin selection bit "0" P13/SDATA2 "1" P13 latch SDATA2 pin selection bit Serial I/O shift register 2 (8) Fig. 36 Block diagram of serial I/O2 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-39 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION Serial I/O2 operation By writing to the serial I/O2 register (address 003116) the serial I/ O2 counter is set to "7". After writing, the SDATA2 pin outputs data every time the transfer clock shifts from "H" to "L". And, as the transfer clock shifts from "L" to "H", the SDATA2 pin reads data, and at the same time the contents of the serial I/O2 register are shifted by 1 bit. When the internal clock is selected as the transfer clock source, the following operations execute as the transfer clock counts up to 8. * Serial I/O2 counter is cleared to "0". * Transfer clock stops at an "H" level. * Interrupt request bit is set. * Shift completion flag is set. Also, the SDATA2 pin is in a high impedance state after the data transfer is completed (refer to Fig.37). When the external clock is selected as the transfer clock source, the interrupt request bit is set as the transfer clock counts up to 8, but external control of the clock is required since it does not stop. Notice that the SDATA2 pin is not in a high impedance state on the completion of data transfer. Also, after the receive operation is completed, the transmit/receive shift completion flag is cleared by reading the serial I/O2 register. At transmit, the transmit/receive shift completion flag is cleared and the transmit operation is started by writing to serial I/O2 register. Synchronous clock Transfer clock Serial I/O2 register write signal (Note) SDATA2 at serial I/O2 output transmit SDATA2 at serial I/O2 input receive D0 D1 D2 D3 D4 D5 D6 D7 Serial I/O2 interrupt request bit set Transmit/receive shift completion flag set Note : When the internal clock is selected as the transfer and the direction register of P1 3/SDATA2 pin is set to the input mode, the SDATA2 pin is in a high impedance state after the data transfer is completed. Fig. 37 Serial I/O2 timing (LSB first) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-40 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION A/D Converter The functional blocks of the A/D converter are described below. [A/D conversion register] AD The A/D conversion register is a read-only register that stores the result of A/D conversion. Do not read out this register during an A/ D conversion. [A/D control register] ADCON The A/D control register controls the A/D converter. Bit 2 to 0 are analog input pin selection bits. Bit 4 is the AD conversion completion bit. The value of this bit remains at "0" during A/D conversion, and changes to "1" at completion of A/D conversion. A/D conversion is started by setting this bit to "0". [Comparison voltage generator] The comparison voltage generator divides the voltage between AVSS and VREF by 1024, and outputs the divided voltages. [Channel selector] The channel selector selects one of ports P27/AN7 to P20/AN0, and inputs the voltage to the comparator. [Comparator and control circuit] The comparator and control circuit compares an analog input voltage with the comparison voltage and stores its result into the A/D conversion register. When A/D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to "1". Because the comparator is constructed linked to a capacitor, set f(XIN) to 500 kHz or more during A/D conversion. s Note on A/D converter As for AD translation accuracy, on the following operating conditions, accuracy may become low. (1) Since the analog circuit inside a microcomputer becomes sensitive to noise when VREF voltage is set up lower than Vcc voltage, accuracy may become low rather than the case where VREF voltage and Vcc voltage are set up to the same value. (2) When VREF voltage is lower than [3.0 V], the accuracy at the low temperature may become extremely low compared with that at room temperature When the system would be used at low temperature, the use at VREF=3.0 V or more is recommended. b7 b0 A/D control register (ADCON : address 003416, initial value: 1016) Analog input pin selection bits 000 : P20/AN0 001 : P21/AN1 010 : P22/AN2 011 : P23/AN3 100 : P24/AN4 101 : P25/AN5 110 : P26/AN6 (Note) 111 : P27/AN7 (Note) Not used (returns "0" when read) AD conversion completion bit 0 : Conversion in progress 1 : Conversion completed Not used (returns "0" when read) Note: These can be used only for 36 pin version. Fig. 38 Structure of A/D control register Read 8-bit (Read only address 003516) b7 (Address 003516) b9 b8 b7 b6 b5 b4 b3 b0 b2 Read 10-bit (read in order address 003616, 003516) b7 (Address 003616) b7 (Address 003516) b7 b6 b5 b4 b3 b2 b1 b9 b0 b8 b0 b0 Note: High-order 6-bit of address 003616 returns "0" when read. Fig. 39 Structure of A/D conversion register Data bus b7 A/D control register (Address 003416) 3 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 A/D control circuit b0 A/D interrupt request Channel selector A/D conversion register (high-order) Comparator (Address 003616) (Address 003516) A/D conversion register (low-order) 10 Resistor ladder VREF VSS Fig. 40 Block diagram of A/D converter Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-41 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION Watchdog Timer The watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. The watchdog timer consists of an 8-bit watchdog timer H and an 8-bit watchdog timer L, being a 16-bit counter. Standard operation of watchdog timer The watchdog timer stops when the watchdog timer control register (address 003916) is not set after reset. Writing an optional value to the watchdog timer control register (address 003916) causes the watchdog timer to start to count down. When the watchdog timer H underflows, an internal reset occurs. Accordingly, it is programmed that the watchdog timer control register (address 003916) can be set before an underflow occurs. When the watchdog timer control register (address 003916) is read, the values of the high-order 6-bit of the watchdog timer H, STP instruction disable bit and watchdog timer H count source selection bit are read. Initial value of watchdog timer By a reset or writing to the watchdog timer control register (address 003916), the watchdog timer H is set to "FF16" and the watchdog timer L is set to "FF16". Operation of watchdog timer H count source selection bit A watchdog timer H count source can be selected by bit 7 of the watchdog timer control register (address 003916). When this bit is "0", the count source becomes a watchdog timer L underflow signal. The detection time is 131.072 ms at f(XIN)=8 MHz. When this bit is "1", the count source becomes f(XIN)/16. In this case, the detection time is 512 s at f(XIN)=8 MHz. This bit is cleared to "0" after reset. Operation of STP instruction disable bit When the watchdog timer is in operation, the STP instruction can be disabled by bit 6 of the watchdog timer control register (address 003916). When this bit is "0", the STP instruction is enabled. When this bit is "1", the STP instruction is disabled, and an internal reset occurs if the STP instruction is executed. Once this bit is set to "1", it cannot be changed to "0" by program. This bit is cleared to "0" after reset. Data bus Write "FF16" to the watchdog timer control register Watchdog timer L (8) 1/16 Write "FF16" to the watchdog timer control register "0" "1" Watchdog timer H (8) XIN Watchdog timer H count source selection bit STP Instruction disable bit STP Instruction Reset circuit Internal reset RESET Fig. 41 Block diagram of watchdog timer b7 b0 Watchdog timer control register (WDTCON: address 003916, initial value: 3F16) Watchdog timer H (read only for high-order 6-bit) STP instruction disable bit 0 : STP instruction enabled 1 : STP instruction disabled Watchdog timer H count source selection bit 0 : Watchdog timer L underflow 1 : f(XIN)/16 Fig. 42 Structure of watchdog timer control register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-42 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION Reset Circuit The microcomputer is put into a reset status by holding the RESET pin at the "L" level for 2 s or more when the power source voltage is 2.2 to 5.5 V and XIN is in stable oscillation. After that, this reset status is released by returning the RESET pin to the "H" level. The program starts from the address having the contents of address FFFD16 as high-order address and the contents of address FFFC16 as low-order address. In the case of f() 6 MHz, the reset input voltage must be 0.9 V or less when the power source voltage passes 4.5 V. In the case of f() 4 MHz, the reset input voltage must be 0.8 V or less when the power source voltage passes 4.0 V. In the case of f() 2 MHz, the reset input voltage must be 0.48 V or less when the power source voltage passes 2.4 V. In the case of f() 1 MHz, the reset input voltage must be 0.44 V or less when the power source voltage passes 2.2 V. RESET VCC Power source voltage 0V Reset input voltage 0V Poweron (Note) 0.2 VCC Note : Reset release voltage Vcc = 2.2 V RESET VCC Power source voltage detection circuit Fig. 43 Example of reset circuit Clock from on-chip oscillator RING RESET RESETOUT SYNC Address Data ? ? ? ? ? ? ? ? ? ? FFFC ADL FFFD ADH,ADL ADH Reset address from the vector table 8-13 clock cycles Notes 1 : An on-chip oscillator applies about RING*2 MHz, *250 kHz frequency clock at average of Vcc = 5 V. 2 : The mark "?" means that the address is changeable depending on the previous state. 3 : These are all internal signals except RESET. Fig. 44 Timing diagram at reset Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-43 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION Address (1) Port P0 direction register (2) Port P1 direction register (3) Port P2 direction register (4) Port P3 direction register (5) Pull-up control register (6) Port P1P3 control register (7) Serial I/O1 status register (8) Serial I/O1 control register (9) UART control register (10) Timer A mode register (11) Timer A (low-order) (12) Timer A (high-order) (13) Timer Y, Z mode register (14) Prescaler Y (15) Timer Y secondary (16) Timer Y primary (17) Timer Y, Z waveform output control register (18) Prescaler Z (19) Timer Z secondary (20) Timer Z primary (21) Prescaler 1 (22) Timer 1 (23) One-shot start register (24) Timer X mode register (25) Prescaler X (26) Timer X (27) Timer count source set register (28) Serial I/O2 control register (29) Serial I/O2 register (30) A/D control register (31) MISRG (32) Watchdog timer control register (33) Interrupt edge selection register (34) CPU mode register (35) Interrupt request register 1 (36) Interrupt request register 2 (37) Interrupt control register 1 (38) Interrupt control register 2 (39) Processor status register (40) Program counter 000116 000316 000516 000716 001616 001716 001916 001A16 001B16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 003016 003116 003416 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 (PS) (PCH) (PCL) X 1 0 1 1 X Register contents 0016 X X 0 0 0 0 0 0016 0016 0016 0016 0 0 0 0 0 0 0 0016 1 1 0 0 0 0 0 0016 FF16 FF16 0016 FF16 FF16 FF16 0016 FF16 FF16 FF16 FF16 0116 0016 0016 FF16 FF16 0016 0016 0016 1016 0016 0 1 1 1 1 1 1 0016 0 0 0 0 0 0 0 0016 0016 0016 0016 X X X X 1 X X Contents of address FFFD16 Contents of address FFFC16 Note X : Undefined Fig. 45 Internal status of microcomputer at reset Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-44 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION Clock Generating Circuit An oscillation circuit can be formed by connecting a resonator between XIN and XOUT, and an RC oscillation circuit can be formed by connecting a resistor and a capacitor. Use the circuit constants in accordance with the resonator manufacturer's recommended values. (1) On-chip oscillator operation When the MCU operates by the on-chip oscillator for the main clock, connect XIN pin to VSS and leave XOUT pin open. The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. (2) Ceramic resonator When the ceramic resonator is used for the main clock, connect the ceramic resonator and the external circuit to pins XIN and XOUT at the shortest distance. A feedback resistor is built in between pins XIN and XOUT. (3) RC oscillation When the RC oscillation is used for the main clock, connect the XIN pin and XOUT pin to the external circuit of resistor R and the capacitor C at the shortest distance. The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits. (4) External clock When the external signal clock is used for the main clock, connect the XIN pin to the clock source and leave XOUT pin open. Select "ceramic resonance" by setting "0" to the Oscillation mode selection bit of CPU mode register (address 003B16). M37540 Note: Externally connect a XIN XOUT Rd CIN COUT damping resistor Rd depending on the oscillation frequency. (A feedback resistor is built-in.) Use the resonator manufacturer's recommended value because constants such as capacitance depend on the resonator. Fig. 46 External circuit of ceramic resonator Note: Connect the external M37540 XIN XOUT circuit of resistor R and the capacitor C at the shortest distance. The frequency is affected by a capacitor, a resistor and a microR computer. So, set the constants C within the range of the frequency limits. Fig. 47 External circuit of RC oscillation M37540 XIN XOUT Open External oscillation circuit VCC VSS Fig. 48 External clock input circuit M37540 XIN Note: The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable freXOUT quencies and obtain the sufficient margin. Open Fig. 49 Processing of XIN and XOUT pins at on-chip oscillator operation Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-45 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION (1) Oscillation control * Stop mode When the STP instruction is executed, the internal clock stops at an "H" level and the XIN oscillator stops. At this time, timer 1 is set to "0116" and prescaler 1 is set to "FF16" when the oscillation stabilization time set bit after release of the STP instruction is "0". On the other hand, timer 1 and prescaler 1 are not set when the above bit is "1". Accordingly, set the wait time fit for the oscillation stabilization time of the oscillator to be used. f(XIN)/16 is forcibly connected to the input of prescaler 1. When an external interrupt is accepted, oscillation is restarted but the internal clock remains at "H" until timer 1 underflows. As soon as timer 1 underflows, the internal clock is supplied. This is because when a ceramic oscillator is used, some time is required until a start of oscillation. In case oscillation is restarted by reset, no wait time is generated. So apply an "L" level to the RESET pin while oscillation becomes stable. Also, the STP instruction cannot be used while CPU is operating by an on-chip oscillator. * Wait mode If the WIT instruction is executed, the internal clock stops at an "H" level, but the oscillator does not stop. The internal clock restarts if a reset occurs or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that interrupts will be received to release the STP or WIT state, interrupt enable bits must be set to "1" before the STP or WIT instruction is executed. s Notes on clock generating circuit For use with the oscillation stabilization set bit after release of the STP instruction set to "1", set values in timer 1 and prescaler 1 after fully appreciating the oscillation stabilization time of the oscillator to be used. * Switch of ceramic and RC oscillations After releasing reset the operation starts by starting an on-chip oscillator. Then, a ceramic oscillation or an RC oscillation is selected by setting bit 5 of the CPU mode register. * Double-speed mode When a ceramic oscillation is selected, a double-speed mode can be used. Do not use it when an RC oscillation is selected. * CPU mode register Bits 5, 1 and 0 of CPU mode register are used to select oscillation mode and to control operation modes of the microcomputer. In order to prevent the dead-lock by error-writing (ex. program run-away), these bits can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. (The emulator MCU "M37540RSS" is excluded.) Also, when the read-modify-write instructions (SEB, CLB) are executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked. * Clock division ratio, XIN oscillation control, on-chip oscillator control The state transition shown in Fig. 52 can be performed by setting the clock division ratio selection bits (bits 7 and 6), XIN oscillation control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of CPU mode register. Be careful of notes on use in Fig. 52. q Oscillation stop detection circuit (Note) The oscillation stop detection circuit is used for reset occurrence when a ceramic resonator or an oscillation circuit stops by disconnection. When internal reset occurs, reset because of oscillation stop can be detected by setting "1" to the oscillation stop detection status bit. Also, when using the oscillation stop detection circuit, an on-chip oscillator is required. Figure 53 shows the state transition. Note: The oscillation stop detection circuit is not included in the emulator MCU "M37540RSS". b7 b0 MISRG(address 003816, initial value: 0016) Oscillation stabilization time set bit after release of the STP instruction 0: Set "0116" in timer1, and "FF16" in prescaler 1 automatically 1: Not set automatically Ceramic or RC oscillation stop detection function active bit 0: Detection function inactive 1: Detection function active Reserved bits (return "0" when read) (Do not write "1" to these bits) Not used (return "0" when read) Oscillation stop detection status bit 0: Oscillation stop not detected 1: Oscillation stop detected Fig. 50 Structure of MISRG Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-46 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION XIN Rf XOUT Clock division ratio selection bit Middle-, high-, low-speed mode 1/2 On-chip oscillator mode 1/4 1/2 Prescaler 1 Timer 1 Clock division ratio selection bit Middle-speed mode High-speed mode RING On-chip oscillator Double-speed mode Timing (Internal clock) 1/8 On-chip oscillator mode QS R STP instruction WIT instruction S R Q Q S R STP instruction Reset Reset Interrupt disable flag l Interrupt request Fig. 51 Block diagram of internal clock generating circuit (for ceramic resonator) XOUT XIN Clock division ratio selection bit Middle-, high-, low-speed mode 1/2 On-chip oscillator mode 1/4 1/2 Prescaler 1 Timer 1 Delay Clock division ratio selection bit Middle-speed mode High-speed mode RING On-chip oscillator Double-speed mode Timing (Internal clock) 1/8 On-chip oscillator mode QS R STP instruction WIT instruction S R Q Q S RESET R STP instruction Reset Interrupt disable flag l Interrupt request Fig. 52 Block diagram of internal clock generating circuit (for RC oscillation) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-47 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION Stop mode Interrupt Interrupt STP instruction Wait mode WIT instruction Interrupt WIT instruction State 2 CPUM76102 Operation clock source: f(XIN) (Note 1) f(XIN) oscillation enabled On-chip oscillator enabled CPUM76002 012 112 (Note 2) State 1 Operation clock source: f(XIN) (Note 1) f(XIN) oscillation enabled On-chip oscillator stop CPUM302 CPUM312 State 3 Operation clock source: On-chip oscillator (Note 3) f(XIN) oscillation enabled On-chip oscillator enalbed CPUM412 CPUM402 State 4 Operation clock source: On-chip oscillator (Note 3) f(XIN) oscillation stop On-chip oscillator enalbed MISRG112 MISRG102 MISRG112 MISRG102 State 2' CPUM76102 Operation clock source: f(XIN) (Note 1) f(XIN) oscillation enabled On-chip oscillator enabled CPUM76002 012 112 (Note 2) State 3' Operation clock source: On-chip oscillator (Note 3) f(XIN) oscillation enabled On-chip oscillator enalbed Oscillation stop detection circuit valid Reset released Reset state Notes on switch of clock (1) In operation clock source = f(XIN), the following can be selected for the CPU clock division ratio. q f(XIN)/2 (high-speed mode) q f(XIN)/8 (middle-speed mode) q f(XIN) (double-speed mode, only at a ceramic oscillation) (2) Execute the state transition state 3 to state 2 or state 3' to state 2' after stabilizing XIN oscillation. (3) In operation clock source = on-chip oscillator, the middlespeed mode is selected for the CPU clock division ratio. (4) When the state transition state 2 state 3 state 4 is performed, execute the NOP instruction as shown below according to the division ratio of CPU clock. * CPUM76 102 (State 2 state 3) * NOP instruction * CPUM4 12 (State 3 state 4) Double-speed mode at on-chip oscillator: NOP 3 High-speed mode at on-chip oscillator: NOP 1 Middle-speed mode at on-chip oscillator: NOP 0 Fig. 53 State transition Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-48 HARDWARE 7540 Group NOTES ON PROGRAMMING/NOTES ON HARDWARE NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after reset are undefined except for the interrupt disable flag I which is "1". After reset, initialize flags which affect program execution. In particular, it is essential to initialize the T flag and the D flag because of their effect on calculations. State transition Do not stop the clock selected as the operation clock because of setting of CM3, 4. NOTES ON HARDWARE Handling of Power Source Pin In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 F to 0.1 F is recommended. Interrupts The contents of the interrupt request bit do not change even if the BBC or BBS instruction is executed immediately after they are changed by program because this instruction is executed for the previous contents. For executing the instruction for the changed contents, execute one instruction before executing the BBC or BBS instruction. One Time PROM Version The CNVss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (VPP pin) as well. To improve the noise reduction, connect a track between CNVss pin and Vss pin with 1 to 10 k resistance. The mask ROM version track of CNVss pin has no operational interference even if it is connected via a resistor. Decimal Calculations * For calculations in decimal notation, set the decimal mode flag D to "1", then execute the ADC instruction or SBC instruction. In this case, execute SEC instruction, CLC instruction or CLD instruction after executing one instruction before the ADC instruction or SBC instruction. * In the decimal mode, the values of the N (negative), V (overflow) and Z (zero) flags are invalid. Ports * The values of the port direction registers cannot be read. That is, it is impossible to use the LDA instruction, memory operation instruction when the T flag is "1", addressing mode using direction register values as qualifiers, and bit test instructions such as BBC and BBS. It is also impossible to use bit operation instructions such as CLB and SEB and read/modify/write instructions of direction registers for calculations such as ROR. For setting direction registers, use the LDM instruction, STA instruction, etc. A/D Conversion Do not execute the STP instruction during A/D conversion. Instruction Execution Timing The instruction execution time can be obtained by multiplying the frequency of the internal clock by the number of cycles mentioned in the machine-language instruction table. The frequency of the internal clock is the same as that of the XIN in double-speed mode, twice the XIN cycle in high-speed mode and 8 times the XIN cycle in middle-speed mode. CPU Mode Register The oscillation mode selection bit and processor mode bits can be rewritten only once after releasing reset. However, after rewriting it is disable to write any value to the bit. (Emulator MCU is excluded.) When a ceramic oscillation is selected, a double-speed mode of the clock division ratio selection bits can be used. Do not use it when an RC oscillation is selected. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-49 HARDWARE 7540 Group NOTES ON PERIPHERAL FUNCTIONS NOTES ON PERIPHERAL FUNCTIONS s Interrupt When setting the followings, the interrupt request bit may be set to "1". *When switching external interrupt active edge Related register: Interrupt edge selection register (address 003A16) Timer X mode register (address 2B16) Timer A mode register (address 1D16) When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. Set the corresponding interrupt enable bit to "0" (disabled). Set the interrupt edge select bit (active edge switch bit). Set the corresponding interrupt request bit to "0" after 1 or more instructions have been executed. Set the corresponding interrupt enable bit to "1" (enabled). s Timer Y: Programmable Generation Waveform Mode * Count set value In the programmable waveform generation mode, values of TYS, EXPYP, and EXPYS are valid by writing to TYP because the setting to them is executed all at once by writing to TYP. Even when changing TYP is not required, write the same value again. * Write timing to TYP In the programmable waveform generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TYP and the timing of timer underflow during the secondary interval simultanesously. * Usage of waveform extension function The waveform extension function by the timer Y waveform extension control bit can be used only when "0016" is set to Prescaler Y. When the value other than "0016" is set to Prescaler Y, be sure to set "0" to EXPYP and EXPYS. * Timer Y write mode When using this mode, be sure to set "1" to the timer Y write control bit to select "write to latch only". Timer Y can stop counting by setting "1" to the timer Y count stop bit in any mode. Also, when Timer Y underflows, the timer Y interrupt request bit is set to "1". Timer Y reloads the value of latch when counting is stopped by the timer Y count stop bit. (When timer is read out while timer is stopped, the value of latch is read. The value of timer can be read out only while timer is operating.) s Timers * When n (0 to 255) is written to a timer latch, the frequency division ratio is 1/(n+1). * When a count source of timer X, timer Y or timer Z is switched, stop a count of timer X. s Timer A CNTR1 interrupt active edge selection CNTR1 interrupt active edge depends on the CNTR1 active edge switch bit. When this bit is "0", the CNTR1 interrupt request bit is set to "1" at the falling edge of the CNTR1 pin input signal. When this bit is "1", the CNTR1 interrupt request bit is set to "1" at the rising edge of the CNTR1 pin input signal. However, in the pulse width HL continuously measurement mode, CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR1 active edge switch bit. s Ti m e r Z : P r o g r a m m a b l e Wa v e f o r m Generation Mode * Count set value In the programmable waveform generation mode, values of TZS, EXPZP, and EXPZS are valid by writing to TZP because the setting to them is executed all at once by writing to TZP. Even when changing TZP is not required, write the same value again. * Write timing to TZP In the programmable waveform generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow during the secondary interval simultanesously. * Usage of waveform extension function The waveform extension function by the timer Z waveform extension control bit can be used only when "0016" is set to Prescaler Z. When the value other than "0016" is set to Prescaler Z, be sure to set "0" to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the count source, the waveform extension function cannot be used. * Timer Z write mode When using this mode, be sure to set "1" to the timer Z write control bit to select "write to latch only". s Timer X CNTR0 interrupt active edge selection CNTR0 interrupt active edge depends on the CNTR0 active edge switch bit. When this bit is "0", the CNTR0 interrupt request bit is set to "1" at the falling edge of CNTR0 pin input signal. When this bit is "1", the CNTR0 interrupt request bit is set to "1" at the rising edge of CNTR0 pin input signal. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-50 HARDWARE 7540 Group NOTES ON PERIPHERAL FUNCTIONS s Ti m e r Z : P r o g r a m m a b l e O n e - s h o t Generation Mode * Count set value In the programmable one-shot generation mode, the value of EXPZP becomes valid by writing to TZP. Even when changing TZP is not required, write the same value again. * Write timing to TZP In the programmable one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow simultanesously. * Usage of waveform extension function The waveform extension function by the timer Z waveform extension control bit can be used only when "0016" is set to Prescaler Z. When the value other than "0016" is set to Prescaler Z, be sure to set "0" to EXPZP. Also, when the timer Y underflow is selected as the count source, the waveform extension function cannot be used. * Timer Z write mode When using this mode, be sure to set "1" to the timer Z write control bit to select "write to latch only". s Serial I/O * Serial I/O interrupt When setting the transmit enable bit to "1", the serial I/O transmit interrupt request bit is automatically set to "1". When not requiring the interrupt occurrence synchronized with the transmission enabled, take the following sequence. Set the serial I/O transmit interrupt enable bit to "0" (disabled). Set the transmit enable bit to "1". Set the serial I/O transmit interrupt request bit to "0" after 1 or more instructions have been executed. Set the serial I/O transmit interrupt enable bit to "1" (enabled). * I/O pin function when serial I/O1 is enabled. The functions of P12 and P13 are switched with the setting values of a serial I/O1 mode selection bit and a serial I/O1 synchronous clock selection bit as follows. (1) Serial I/O1 mode selection bit "1" : Clock synchronous type serial I/O is selected. Setup of a serial I/O1 synchronous clock selection bit "0" : P12 pin turns into an output pin of a synchronous clock. "1" : P12 pin turns into an input pin of a synchronous clock. Setup of a SRDY1 output enable bit (SRDY) "0" : P13 pin can be used as a normal I/O pin. "1" : P13 pin turns into a SRDY output pin. (2) Serial I/O1 mode selection bit "0" : Clock asynchronous (UART) type serial I/O is selected. Setup of a serial I/O1 synchronous clock selection bit "0": P12 pin can be used as a normal I/O pin. "1": P12 pin turns into an input pin of an external clock. When clock asynchronous (UART) type serial I/O is selected, it is P13 pin. It can be used as a normal I/O pin. s Timer Z: Programmable Wait One-shot Generation Mode * Count set value In the programmable wait one-shot generation mode, values of TZS, EXPZP and EXPZS are valid by writing to TZP. Even when changing TZP is not required, write the same value again. * Write timing to TZP In the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow during the secondary interval simultanesously. * Usage of waveform extension function The waveform extension function by the timer Z waveform extension control bit can be used only when "0016" is set to Prescaler Z. When the value other than "0016" is set to Prescaler Z, be sure to set "0" to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the count source, the waveform extension function cannot be used. * Timer Z write mode When using this mode, be sure to set "1" to the timer Z write control bit to select "write to latch only". Timer Z can stop counting by setting "1" to the timer Z count stop bit in any mode. Also, when Timer Z underflows, the timer Z interrupt request bit is set to "1". Timer Z reloads the value of latch when counting is stopped by the timer Z count stop bit. (When timer is read out while timer is stopped, the value of latch is read. The value of timer can be read out only while timer is operating.) s A/D Converter * The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(XIN) is 500kHz or more during A/D conversion. * As for AD translation accuracy, on the following operating conditions, accuracy may become low. (1) Since the analog circuit inside a microcomputer becomes sensitive to noise when VREF voltage is set up lower than Vcc voltage, accuracy may become low rather than the case where VREF voltage and Vcc voltage are set up to the same value. (2) When VREF voltage is lower than [3.0 V], the accuracy at the low temperature may become extremely low compared with that at room temperature When the system would be used at low temperature, the use at VREF=3.0 V or more is recommended. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-51 HARDWARE 7540 Group NOTES ON PERIPHERAL FUNCTIONS s Notes on clock generating circuit For use with the oscillation stabilization set bit after release of the STP instruction set to "1", set values in timer 1 and prescaler 1 after fully appreciating the oscillation stabilization time of the oscillator to be used. * Switch of ceramic and RC oscillations After releasing reset the operation starts by starting an on-chip oscillator. Then, a ceramic oscillation or an RC oscillation is selected by setting bit 5 of the CPU mode register. * Double-speed mode When a ceramic oscillation is selected, a double-speed mode can be used. Do not use it when an RC oscillation is selected. * CPU mode register Bits 5, 1 and 0 of CPU mode register are used to select oscillation mode and to control operation modes of the microcomputer. In order to prevent the dead-lock by error-writing (ex. program run-away), these bits can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. (The emulator MCU "M37540RSS" is excluded.) Also, when the read-modify-write instructions (SEB, CLB) are executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked. * Clock division ratio, XIN oscillation control, on-chip oscillator control The state transition shown in Fig. 53 can be performed by setting the clock division ratio selection bits (bits 7 and 6), XIN oscillation control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of CPU mode register. Be careful of notes on use in Fig. 53. * On-chip oscillator operation The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. s Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. s Electric Characteristic Differences Among Mask ROM and One TIme PROM Version MCUs There are differences in electric characteristics, operation margin, noise immunity, and noise radiation among mask ROM and One Time PROM version MCUs due to the differences in the manufacturing processes. When manufacturing an application system with One Time PROM version and then switching to use of the mask ROM version, perform sufficient evaluations for the commercial samples of the mask ROM version. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-52 HARDWARE 7540 Group DATA REQUIRED FOR MASK ORDERS/DATA REQUIRED FOR ROM PROGRAMMING ORDERS/ ROM PROGRAMMING METHOD DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: 1.Mask ROM Order Confirmation Form * 2.Mark Specification Form * 3.Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk. ROM PROGRAMMING METHOD The built-in PROM of the blank One Time PROM version can be read or programmed with a general-purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. Table 7 Special programming adapter Package 32P4B 32P6U-A 36P2R-A Name of Programming Adapter PCA7435SPG02 PCA7435GPG03 PCA7435FPG02 DATA REQUIRED FOR ROM PROGRAMMING ORDERS The following are necessary when ordering a One Time PROM production: 1.ROM Programming Order Confirmation Form * 2.Mark Specification Form * 3.Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk. * For the mask ROM confirmation ROM programming order confirmation and the mark specifications, refer to the "Renesas Technology Corp" Homepage (http://www.renesas.com/en/rom). The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 54 is recommended to verify programming. Programming with PROM programmer Screening (Caution) (150 C for 40 hours) Verification with PROM programmer Functional check in target device Caution: The screening temperature is far higher than the storage temperature. Never expose to 150 C exceeding 100 hours. Fig. 54 Programming and testing of One Time PROM version Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-53 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION SUPPLEMENT FUNCTIONAL SUPPLEMENT Interrupt DESCRIPTION 7540 group permits interrupts on the 14 sources for 42-pin version, 13 sources for 36-pin version and 12 sources for 32-pin version. It is vector interrupts with a fixed priority system. Accordingly, when two or more interrupt requests occur during the same sampling, the higher-priority interrupt is accepted first. This priority is determined by hardware, but variety of priority processing can be performed by software, using an interrupt enable bit and an interrupt disable flag. For interrupt sources, vector addresses and interrupt priority, refer to "Table 8." Table 8 Interrupt sources, vector addresses and interrupt priority Interrupt source Priority Reset (Note 2) Serial I/O1 receive Serial I/O1 transmit INT0 INT1 (Note 3) Key-on wake-up CNTR0 CNTR1 Timer X Timer Y Timer Z Timer A Serial I/O2 A/D conversion Timer 1 Reserved area BRK instruction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Vector addresses (Note 1) High-order FFFD16 FFFB16 FFF916 FFF716 FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDF16 FFDD16 Low-order FFFC16 FFFA16 FFF816 FFF616 FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDE16 FFDC16 Interrupt request generating conditions At reset input At completion of serial I/O1 data receive At completion of serial I/O1 transmit shift or when transmit buffer is empty At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At falling of conjunction of input logical level for port P0 (at input) At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At timer X underflow At timer Y underflow At timer Z underflow At timer A underflow At completion of transmit/receive shift At completion of A/D conversion At timer 1 underflow Not available At BRK instruction execution Remarks Non-maskable Valid only when serial I/O1 is selected Valid only when serial I/O1 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (valid at falling) External interrupt (active edge selectable) External interrupt (active edge selectable) STP release timer underflow Non-maskable software interrupt Note 1: Vector addressed contain internal jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 3: It is an interrupt which can use only for 36 pin version. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-54 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION SUPPLEMENT Timing After Interrupt The interrupt processing routine begins with the machine cycle following the completion of the instruction that is currently in execution. Figure 55 shows a timing chart after an interrupt occurs, and Figure 56 shows the time up to execution of the interrupt processing routine. SYNC RD WR Address bus Data bus PC Not used S, SPS S-1, SPS S-2, SPS BL AL BH AL, AH AH PCH PCL PS SYNC : CPU operation code fetch cycle BL, BH : Vector address of each interrupt AL, AH : Jump destination address of each interrupt SPS : "0016" or "0116" Fig. 55 Timing chart after an interrupt occurs Generation of interrupt request Start of interrupt processing Main routine Waiting time for post-processing of pipeline Stack push and Vector fetch Interrupt processing routine 0 to 16 cycles 2 cycles 5 cycles 7 to 23 cycles (At performing 6.0 MHz, in double-speed mode, 1.75 s to 5.75 s) Fig. 56 Time up to execution of the interrupt processing routine Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-55 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION SUPPLEMENT A/D Converter A/D conversion is started by setting AD conversion completion bit to "0." During A/D conversion, internal operations are performed as follows. 1. After the start of A/D conversion, A/D conversion register goes to "0016." 2. The highest-order bit of A/D conversion register is set to "1," and the comparison voltage Vref is input to the comparator. Then, Vref is compared with analog input voltage VIN. 3. As a result of comparison, when Vref < VIN, the highest-order bit of A/D conversion register becomes "1." When Vref > VIN, the highest-order bit becomes "0." By repeating the above operations up to the lowestorder bit of the A/D conversion register, an analog value converts into a digital value. A/D conversion completes at 122 clock cycles (20.34 s at f(XIN) = 6.0 MHz) after it is started, and the result of the conversion is stored into the A/D conversion register. Concurrently with the completion of A/D conversion, A/D conversion interrupt request occurs, so that the AD conversion interrupt request bit is set to "1." Relative formula for a reference voltage VREF of A/D converter and Vref When n = 0 When n = 1 to 1023 Vref = 0 Vref = VREF n 1024 n : the value of A/D converter (decimal numeral) Table 9 Change of A/D conversion register during A/D conversion Change of A/D conversion register At start of conversion First comparison Second comparison Third comparison * * * After completion of tenth comparison Value of comparison voltage (Vref) 0 0 0 0 VREF 2 VREF 2 VREF 2 VREF VREF 8 0 0 1 1 1 0 0 1 2 0 0 0 1 0 0 0 0 0 0 0 0 * * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 VREF 4 * * * A result of A/D conversion 1 2 3 4 5 6 7 8 9 10 VREF 2 VREF 4 *** VREF 1024 1-10: A result of the first to tenth comparison Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-56 HARDWARE 7540 Group FUNCTIONAL DESCRIPTION SUPPLEMENT Figure 56 shows A/D conversion equivalent circuit, and Figure 57 shows A/D conversion timing chart. VCC (Note 1) R 1.5 k(Typical) ANi (i=0 to 7: 36-pin version i=0 to 5: 32-pin version) C2 1.5 pF(Typical) SW1 (Note 2) (Note 1) Typical voltage generation circuit Switch tree, ladder resistor Chopper Amp. C1 12 pF(Typical) VSS VSS Notes 1: This is a parasitic diode. 2: Only the selected analog input pin is turned on. A/D control circuit VSS VREF Fig. 57 A/D conversion equivalent circuit XIN Write signal for A/D control register 122 XIN cycles AD conversion completion bit Sampling clock Fig. 58 A/D conversion timing chart Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 1-57 CHAPTER 2 APPLICATION 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 I/O port Timer A Timer 1 Timer X Timer Y and timer Z Serial I/O1 Serial I/O2 A/D converter Reset APPLICATION 7540 Group 2.1 I/O port 2.1 I/O port This paragraph explains the registers setting method and the notes relevant to the I/O ports. 2.1.1 Memory map 000016 000116 000216 000316 000416 000516 000616 000716 001616 001716 003A16 003C16 003E16 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Pull-up control register (PULL) Port P1P3 control register (P1P3C) Interrupt edge selection register (INTEDGE) Interrupt request register 1 (IREQ1) Interrupt control register 1 (ICON1) Fig. 2.1.1 Memory map of registers relevant to I/O port Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-2 APPLICATION 7540 Group 2.1 I/O port 2.1.2 Relevant registers Port Pi b7 b6 b5 b4 b3 b2 b1 b0 Port Pi (Pi) (i = 0, 2, 3) [Address : 00 16, 0416, 0616] B 0 Port Pi0 1 Port Pi1 Name q Function In output mode Write Port latch Read In input mode Write : Port latch Read : Value of pins At reset RW ? ? ? ? ? ? ? ? q 2 Port Pi2 3 Port Pi3 4 Port Pi4 5 Port Pi5 6 Port Pi6 7 Port Pi7 Note: The 32-pin package versions have nothing to be allocated for the following: *Bits 6 and 7 of port P2 *Bits 5 and 6 of port P3. Fig. 2.1.2 Structure of Port Pi (i = 0, 2, 3) Port P1 b7 b6 b5 b4 b3 b2 b1 b0 Port P1 (P1) [Address : 02 16] B 0 Port P10 1 Port P11 Name q Function In output mode Write Port latch Read In input mode Write : Port latch Read : Value of pins At reset RW ? ? ? ? ? ? ? ? q 2 Port P12 3 Port P13 4 Port P14 5 Nothing is allocated for these bits. When these bits are read out, the values are undefined. 6 7 Fig. 2.1.3 Structure of Port P1 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-3 APPLICATION 7540 Group 2.1 I/O port Port Pi direction register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (PiD) (i = 0, 2, 3) [Address : 01 16, 0516, 0716] At reset B Name Function 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode RW 0 Port Pi direction register 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 Note: The 32-pin package versions have nothing to be allocated for the following: *Bits 6 and 7 of P2D *Bits 5 and 6 of P3D. Fig. 2.1.4 Structure of Port Pi direction register (i = 0, 2, 3) Port P1 direction register b7 b6 b5 b4 b3 b2 b1 b0 Port P1 direction register (P1D) [Address : 03 16] B Name Function 0 : Port P10 input mode 1 : Port P10 output mode 0 : Port P11 input mode 1 : Port P11 output mode 0 : Port P12 input mode 1 : Port P12 output mode 0 : Port P13 input mode 1 : Port P13 output mode 0 : Port P14 input mode 1 : Port P14 output mode At reset RW 0 Port P1 direction register 1 2 3 4 0 0 0 0 0 ? ? ? 5 Nothing is allocated for these bits. When these bits are read out, the values are undefined. 6 7 Fig. 2.1.5 Structure of Port P1 direction register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-4 APPLICATION 7540 Group 2.1 I/O port Pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 Pull-up control register (PULL) [Address : 1616] Name B 0 P00 pull-up control bit 1 P01 pull-up control bit 2 P02, P03 pull-up control bit 3 P04 - P07 pull-up control bit 4 P30 - P33 pull-up control bit 5 P34 pull-up control bit 6 P35, P36 pull-up control bit 7 P37 pull-up control bit Function 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On At reset RW 0 0 0 0 0 0 0 0 Note: Pins set to output are disconnected from the pull-up control. Fig. 2.1.6 Structure of Pull-up control register Port P1P3 control register b7 b6 b5 b4 b3 b2 b1 b0 Port P1P3 control register (P1P3C) [Address : 17 16] B bit Name Function 0 : CMOS level 1 : TTL level 0 : CMOS level 1 : TTL level 0 : CMOS level 1 : TTL level At reset RW 0 P37/INT0 input level selection 1 P36/INT1 input level selection bit (Note) 2 P10, P12,P13 input level selection bit 0 0 0 0 0 0 0 0 3 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 4 5 6 7 Note: Keep setting the P3 6/INT1 input level selection bit to "0" (initial value) for the 32-pin package version. Fig. 2.1.7 Structure of Port P1P3 control register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-5 APPLICATION 7540 Group 2.1 I/O port Interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt edge selection register (INTEDGE) [Address : 3A 16] B Name Function 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active At reset RW 0 INT0 interrupt edge selection bit 1 INT1 interrupt edge selection bit 0 0 0 0 0 0 0 2 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 3 4 5 6 7 P00 key-on wakeup enable bit 0 : Key-on wakeup enabled 1 : Key-on wakeup disabled 0 Fig. 2.1.8 Structure of Interrupt edge selection register Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address : 3C 16] B Name Function 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset RW 0 Serial I/O1 receive interrupt request bit 1 Serial I/O1 transmit interrupt request bit 0 0 0 0 0 0 0 0 2 INT0 interrupt request bit 3 INT1 interrupt request bit 4 Key-on wake up interrupt request bit 5 CNTR0 interrupt request bit 6 CNTR1 interrupt request bit 7 Timer X interrupt request bit : These bits can be cleared to "0" by program, but cannot be set to "1". Fig. 2.1.9 Structure of Interrupt request register 1 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-6 APPLICATION 7540 Group 2.1 I/O port Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address : 3E 16] B Name Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset RW 0 Serial I/O1 receive interrupt enable bit 1 Serial I/O1 transmit interrupt enable bit 2 INT0 interrupt enable bit 3 INT1 interrupt enable bit 4 Key-on wake up interrupt enable bit 0 0 0 0 0 0 0 0 5 CNTR0 interrupt enable bit 6 CNTR1 interrupt enable bit 7 Timer X interrupt enable bit Fig. 2.1.10 Structure of Interrupt control register 1 2.1.3 Application example of key-on wake up (1) Outline: The built-in pull-up resistor is used. Specifications: System is returned from the wait mode when the key-on wakeup interrupt occurs by input of the falling edge to port P0i. Note: Only the falling edge is active for the key-on wakeup interrupt. Figure 2.1.11 shows an example of application circuit, and Figure 2.1.12 shows an example of control procedure. 7540 Group P03 P0i(i:0 to 3) P02 Key ON P01 P00 Fig. 2.1.11 Example of application circuit Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-7 APPLICATION 7540 Group 2.1 I/O port RESET Initialization X: This bit is not used here. Set it to "0" or "1" arbitrary. SEI CLD CLT 10000X002 CPUM (Address 3B16) Wait until f(XIN) oscillation is stabilized (Note) XX000X002 CPUM (Address 3B16) Note: For the concrete time, ask the oscillator manufacture. Set pull-up control register 111 PULL(Address 1616) P00 pull-up On P01 pull-up On P02,P03 pull-up On CLI Power-down processing Set interrupt edge selection register 0 INTEDGE(Address 3A16) Key-on wakeup enabled Set "0" to the key-on wakeup interrupt request bit. Set "1" to the key-on wakeup interrupt enable bit. (key-on wakeup interrupt enabled) WIT Processing continued Key ON Key-on wakeup interrupt processing * * * * * * RTI Fig. 2.1.12 Example of control procedure (1) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-8 APPLICATION 7540 Group 2.1 I/O port 2.1.4 Application example of key-on wake up (2) Outline: The key-on wakeup interrupt is used as the normal external interrupt. Specifications: The key-on wakeup interrupt occurs by input of the falling edge to port P0i. If necessary, the built-in pull-up resistor is used. Note: Only the falling edge is active for the key-on wakeup interrupt. Figure 2.1.13 shows an example of control procedure. RESET Initialization SEI CLD CLT CPUM(Address 3B16) 10000X002 Wait until f(XIN) oscillation is stabilized (Note 1) CPUM(Address 3B16) XX000X002 X: This bit is not used here. Set it to "0" or "1" arbitrary. Set port P0i using key-on wakeup interrupt to input mode. Set port not using key-on wakeup interrupt to output mode. Set pull-up control register, if necessary PULL(Address 1616) P00 pull-up On/Off P01 pull-up On/Off P02,P03 pull-up On/Off P04-P07 pull-up On/Off Set interrupt edge selection register (Note 2) INTEDGE(Address 3A16) 0 Key-on wakeup enabled Notes 1: For the concrete time, ask the oscillator manufacture. 2: In this case, port P00 is used. Set "0" to the key-on wakeup interrupt request bit. Set "1" to the key-on wakeup interrupt enable bit. (key-on wakeup interrupt enabled) CLI Key-on waleup interrupt processing routine Processing Processing RTI Fig. 2.1.13 Example of control procedure (2) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-9 APPLICATION 7540 Group 2.1 I/O port 2.1.5 Handling of unused pins Table 2.1.1 Handling of unused pins Pins/Ports name P0, P1, P2, P3 Handling *Set to the input mode and connect each to Vcc or Vss through a resistor of 1 k to 10 k. *Set to the output mode and open at "L" or "H" level. *Connect to Vss (GND). *Connect to VSS (GND) when using an on-chip oscillator for main clock. *Open when using an external clock. *Open when using an on-chip oscillator for main clock. VREF XIN XOUT Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-10 APPLICATION 7540 Group 2.1 I/O port 2.1.6 Notes on input and output ports Notes on using input and output ports are described below. (1) Notes in stand-by state In stand-by state* 1 for low-power dissipation, do not make input levels of an input port and an I/O port "undefined". Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a resistor. When determining a resistance value, note the following points: * External circuit * Variation of output levels during the ordinary operation When using a built-in pull-up resistor, note on varied current values: * When setting as an input port : Fix its input level * When setting as an output port : Prevent current from flowing out to external. q Reason The output transistor becomes the OFF state, which causes the ports to be the high-impedance state. Note that the level becomes "undefined" depending on external circuits. Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of a input port and an I/O port are "undefined". This may cause power source current. * 1 stand-by state : the stop mode by executing the STP instruction the wait mode by executing the WIT instruction (2) Modifying output data with bit managing instruction When the port latch of an I/O port is modified with the bit managing instruction*2, the value of the unspecified bit may be changed. q Reason The bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an I/O port, the following is executed to all bits of the port latch. * As for a bit which is set for an input port : The pin state is read in the CPU, and is written to this bit after bit managing. * As for a bit which is set for an output port : The bit value of the port latch is read in the CPU, and is written to this bit after bit managing. Note the following : * Even when a port which is set as an output port is changed for an input port, its port latch holds the output data. * As for a bit of the port latch which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents. * 2 bit managing instructions : SEB, and CLB instructions (3) Usage for the 32-pin version Fix the P35, P36 pull-up control bit of the pull-up control register to "1". Keep the P36/INT1 input level selection bit of the port P1P3 control register "0" (initial state). Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-11 APPLICATION 7540 Group 2.1 I/O port 2.1.7 Termination of unused pins (1) Terminate unused pins I/O ports : * Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of 1 k to 10 k. Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the I/ O ports for the output mode and open them at "L" or "H". * When opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side. * Since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. (2) Termination remarks Input ports and I/O ports : Do not open in the input mode. q Reason * The power source current may increase depending on the first-stage circuit. * An effect due to noise may be easily produced as compared with proper termination and shown on the above. I/O ports : When setting for the input mode, do not connect to VCC or VSS directly. q Reason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and VCC (or VSS). I/O ports : When setting for the input mode, do not connect multiple ports in a lump to VCC or VSS through a resistor. q Reason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. * At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-12 APPLICATION 7540 Group 2.2 Timer A 2.2 Timer A This paragraph explains the registers setting method and the notes relevant to the timer A. 2.2.1 Memory map 000116 Port P0 direction register (P0D) Pull-up control register (PULL) Timer A mode register (TAM) Timer A (low-order) (TAL) Timer A (high-order) (TAH) 001616 001D16 001E16 001F16 003A16 Interrupt edge selection register (INTEDGE) 003C16 003D16 003E16 003F16 Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Fig. 2.2.1 Memory map of registers relevant to timer A Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-13 APPLICATION 7540 Group 2.2 Timer A 2.2.2 Relevant registers Port P0 direction register b7 b6 b5 b4 b3 b2 b1 b0 Port P0 direction register (P0D) [Address : 01 16] B Name Function 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode At reset RW 0 Port P0 direction register 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 Fig. 2.2.2 Structure of Port P0 direction register Pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 Pull-up control register (PULL) [Address : 1616] Name B 0 P00 pull-up control bit 1 P01 pull-up control bit 2 P02, P03 pull-up control bit 3 P04 - P07 pull-up control bit 4 P30 - P33 pull-up control bit 5 P34 pull-up control bit 6 P35, P36 pull-up control bit 7 P37 pull-up control bit Function 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On At reset RW 0 0 0 0 0 0 0 0 Note: Pins set to output are disconnected from the pull-up control. Fig. 2.2.3 Structure of Pull-up control register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-14 APPLICATION 7540 Group 2.2 Timer A Timer A mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer A mode register (TAM) [Address : 1D 16] B Name Function At reset RW 0 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 0 0 0 0 1 2 3 4 Timer A operating mode bits 5 6 CNTR1 active edge switch bit b5 b4 0 0 1 1 0 : Timer mode 1 : Period measurement mode 0 : Event counter mode 1 : Pulse width HL continuously measurement mode 0 0 0 The function depends on the operating mode. (Refer to Table 2.2.1) 0 : Count start 1 : Count stop 7 Timer A count stop bit 0 Fig. 2.2.4 Structure of Timer A mode register Table 2.2.1 CNTR1 active edge switch bit function Timer A operating modes Timer mode CNTR1 active edge switch bit (bit 6 of address 1D16) contents "0" CNTR1 interrupt request occurrence: Falling edge ; No influence to timer count "1" CNTR1 interrupt request occurrence: Rising edge Period measurement mode ; No influence to timer count "0" Period measurement: Falling period measurement CNTR1 interrupt request occurrence: Falling edge "1" Period measurement: Rising period measurement CNTR1 interrupt request occurrence: Rising edge Event counter mode "0" Timer A: Rising edge count CNTR1 interrupt request occurrence: Falling edge "1" Timer A: Falling edge count CNTR1 interrupt request occurrence: Rising edge P u l s e w i d t h H L c o n t i n u o u s l y "0" CNTR1 interrupt request occurrence: Rising edge and Falling edge measurement mode "1" CNTR1 interrupt request occurrence: Rising edge and Falling edge Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-15 APPLICATION 7540 Group 2.2 Timer A Timer A register (low-order, high-order) b7 b6 b5 b4 b3 b2 b1 b0 Timer A register (low-order, high-order) (TAL, TAH) [Address : 1E 16, 1F16] At reset B Function RW 0 *Set a count value of timer A. *The value set in this register is written to both timer A and timer A 1 latch at the same time. *When this register is read out, the timer A's count value is read 2 out. 1 1 1 1 1 1 1 1 3 4 5 6 7 Notes 1: Be sure to write to/read out both the low-order of timer A (TAL) and the highorder of timer A (TAH). 2: Read the high-order of timer A (TAH) first, and the high-order of timer A (TAL) next. 3: Write to the low-order of timer A (TAL) first, and the high-order of timer A (TAH) next. 4: Do not write to them during read, and do not read out them during write. Fig. 2.2.5 Structure of Timer A register Interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt edge selection register (INTEDGE) [Address : 3A 16] B Name Function 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active At reset RW 0 INT0 interrupt edge selection bit 1 INT1 interrupt edge selection bit 0 0 0 0 0 0 0 2 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 3 4 5 6 7 P00 key-on wakeup enable bit 0 : Key-on wakeup enabled 1 : Key-on wakeup disabled 0 Fig. 2.2.6 Structure of Interrupt edge selection register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-16 APPLICATION 7540 Group 2.2 Timer A Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address : 3C 16] B Name Function 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset RW 0 Serial I/O1 receive interrupt request bit 1 Serial I/O1 transmit interrupt request bit 2 INT0 interrupt request bit 3 INT1 interrupt request bit 4 Key-on wake up interrupt request bit 5 CNTR0 interrupt request bit 0 0 0 0 0 0 0 0 6 CNTR1 interrupt request bit 7 Timer X interrupt request bit : These bits can be cleared to "0" by program, but cannot be set to "1". Fig. 2.2.7 Structure of Interrupt request register 1 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2) [Address : 3D 16] B Name Function 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset RW 0 Timer Y interrupt request bit 1 Timer Z interrupt request bit 2 Timer A interrupt request bit 3 Serial I/O2 interrupt request bit 4 AD converter interrupt request bit 0 0 0 0 0 0 0 0 5 Timer 1 interrupt request bit 6 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 7 : These bits can be cleared to "0" by program, but cannot be set to "1". Fig. 2.2.8 Structure of Interrupt request register 2 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-17 APPLICATION 7540 Group 2.2 Timer A Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address : 3E 16] B Name Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset RW 0 Serial I/O1 receive interrupt enable bit 1 Serial I/O1 transmit interrupt enable bit 2 INT0 interrupt enable bit 3 INT1 interrupt enable bit 4 Key-on wake up interrupt enable bit 0 0 0 0 0 0 0 0 5 CNTR0 interrupt enable bit 6 CNTR1 interrupt enable bit 7 Timer X interrupt enable bit Fig. 2.2.9 Structure of Interrupt control register 1 Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 2 (ICON2) [Address : 3F 16] B Name Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset RW 0 Timer Y interrupt enable bit 1 Timer Z interrupt enable bit 2 Timer A interrupt enable bit 3 Serial I/O2 interrupt enable bit 4 AD conversion interrupt enable bit 5 Timer 1 interrupt enable bit 0 0 0 0 0 0 0 0 6 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 7 Fig. 2.2.10 Structure of Interrupt control register 2 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-18 APPLICATION 7540 Group 2.2 Timer A 2.2.3 Timer mode (1) Operation description Timer A counts the oscillation frequency divided by 16. Each time the count clock is input, the contents of Timer A is decremented by 1. When the contents of Timer A reach "000016", an underflow occurs at the next count clock, and the timer A latch is reloaded into Timer A. The division ratio of Timer A is 1/(n+1) provided that the value of Timer A is n. Timer A can stop counting by setting "1" to the timer A count stop bit. Also, when Timer A underflows, the timer A interrupt request bit is set to "1". (2) Timer mode setting method Figure 2.2.11 shows the setting method for timer mode of timer A. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-19 APPLICATION 7540 Group 2.2 Timer A Process 1: Disable timer A interrupt. b7 b0 0 Interrupt control register 2 (ICON2) [Address 3F16] Timer A interrupt disabled Process 2: Set timer A mode register. b7 b0 1 00 Timer A mode register (TAM) [Address 1D16] Timer mode Timer A count stop Process 3: Set the count value to Timer A (Note). * Set the count value to timer A (low-order) Timer A (low-order) (TAL) (Address 1E16) Count value * Set the count value to timer A (high-order) Timer A (high-order) (TAH) (Address 1F16) Count value Note: Write both registers in order of timer X (low-order) and timer X (high-order) following, certainly. Process 4: In order not to execute the no requested interrupt processing, set "0" (no requested) to the timer A interrupt request bit. b7 b0 0 Interrupt request register 2 (IREQ2) [Address 3D16] No timer A interrupt request issued Process 5: When Timer A interrupt is used, set "1" (interrupt enabled) to the timer A interrupt enable bit. b7 b0 1 Interrupt control register 2 (ICON2) [Address 3F16] Timer A interrupt enabled Process 6: Start counting of Timer A. b7 b0 0 00 Timer A mode register (TAM) [Address 1D16] Timer A count start Fig. 2.2.11 Setting method for timer mode Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-20 APPLICATION 7540 Group 2.2 Timer A (3) Application example of timer mode Outline: The input clock is divided by the timer so that the period processing is executed every 25 ms intervals. Specifications: *The f(XIN) = 8 MHz is divided by timer A to detect 25 ms. *The timer A interrupt request is confirmed in the main routine. When 25 ms has elapsed, the period processing is executed in the timer A interrupt processing routine. * Operation clock: f(XIN) = 8 MHz, high-speed mode Figure 2.2.12 shows an example of control procedure. RESET Initialization SEI CLD CLT CPUM(Address 3B16) 10000X002 Wait until f(XIN) oscillation is stabilized (Note 1) CPUM(Address 3B16) 00000X002 X: This bit is not used here. Set it to "0" or "1" arbitrary. Set "0" to the timer A interrupt enable bit. (Timer A interrupt disabled) Set timer A mode register 1 00 TAM(Address 1D16) Timer mode Timer A count stop Notes 1: For the concrete time, ask the oscillator manufacture. 2: When setting the value to Timer A, set in order of low-order byte and high-order byte following. 3: 25 ms = 1/8 MHz 16 (30D316 + 1) Timer A division ratio (fixed) Timer A setting value Set value to timer A (Notes 2, 3) "D316" "3016" Timer A (low-order) (Address 1E16) Timer A (high-order) (Address 1F16) Set "0" to the timer A interrupt request bit. Set "1" to the timer A interrupt enable bit. (Timer A interrupt enabled) Set timer A mode register 0 00 TAM(Address 1D16) Timer A count start CLI Timer A interrupt processing routine Processing Periodic processing RTI Fig. 2.2.12 Example of control procedure Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-21 APPLICATION 7540 Group 2.2 Timer A 2.2.4 Period measurement mode (1) Operation description In the period measurement mode, the pulse period input from the P00/CNTR1 pin is measured. CNTR1 interrupt request is generated at rising/falling edge of CNTR1 pin input signal. Simultaneously, the value in the timer A latch is reloaded in Timer A and count continues. The active edge of CNTR1 pin input signal can be selected from rising or falling by the CNTR1 active edge switch bit. The count value when trigger input from CNTR1 pin is accepted is retained until Timer A is read once. Timer A can stop counting by setting "1" to the timer A count stop bit. Also, when Timer A underflows, the timer A interrupt request bit is set to "1". (2) Period measurement mode setting method Figure 2.2.13 and Figure 2.2.14 show the setting method for period measurement mode of timer A. Process 1: Disable timer A interrupt and CNTR1 interrupt. b7 b0 0 Interrupt control register 1 (ICON1) [Address 3E16] CNT R1 interrupt disabled b7 b0 0 Interrupt control register 2 (ICON2) [Address 3F16] Timer A interrupt disabled Process 2: Set the CNTR1 pin to the input mode. b7 b0 0 Port P0 direction register (P0D) [Address 0116] Set the P00/CNTR1 pin to the input mode Process 3: Set pull-up control register. b7 b0 Pull-up control register (PULL) [Address 1616] P00/CNTR1 pull-up control bit 0: Pull-up Off 1: Pull-up On Process 4: Set timer A mode register. b7 b0 1 01 Timer A mode register (TAM) [Address 1D16] Period measurement mode CNT R1 active edge selected 0: Falling period measured Falling edge active for CNTR1 interrupt 1: Rising period measured Rising edge active for CNT R1 interrupt Timer A count stop Fig. 2.2.13 Setting method for period measurement mode (1) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-22 APPLICATION 7540 Group 2.2 Timer A Process 5: Set the count value to timer A (Note). * Set the initial value to timer A (low-order) Timer A (low-order) (TAL) (Address 1E16) Initial value * Set the initial value to timer A (high-order) Timer A (high-order) (TAH) (Address 1F16) Initial value Note: Write both registers in order of timer X (low-order) and timer X (high-order) following, certainly. Process 6: In order to use the CNTR1 pin function of the P00/CNTR1 pin, disable the P00 key-on wakeup function. b7 b0 1 Interrupt edge selection register (INTEDGE) [Address 3A16] Key-on wakeup disabled Process 7: In order not to execute the no requested interrupt processing, set "0" (no requested) to the timer A interrupt request bit and CNTR1 interrupt request bit. b7 b0 0 Interrupt request register 1 (IREQ1) [Address 3C16] No CNTR1 interrupt request issued b7 b0 0 Interrupt request register 2 (IREQ2) [Address 3D16] No timer A interrupt request issued Process 8: When the interrupt is used, set "1" (interrupt enabled) to the timer A interrupt enable bit or CNTR1 interrupt enable bit. b7 b0 1 Interrupt control register 1 (ICON1) [Address 3E16] CNTR1 interrupt enabled b7 b0 1 Interrupt control register 2 (ICON2) [Address 3F16] Timer A interrupt enabled Process 9: Start counting of timer A. b7 b0 0 01 Timer A mode register (TAM) [Address 1D16] Timer A count start Fig. 2.2.14 Setting method for period measurement mode (2) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-23 APPLICATION 7540 Group 2.2 Timer A (3) Application example of period measurement mode Outline: The phase control signal is adjusted by using the period measurement mode. Specifications: * The phase control signal is output to a load, and that controls the phase of a load. * The period of the pulse input to the P00/CNTR1 pin from the load as a feedback signal is measured. The correct of the phase control signal to the load is executed using this result. The input pulse period is set to be less than the period of timer A. When timer A underflows, the period is recognized as not corrected, and error processing is executed in the timer A interrupt processing routine. * Operation clock: f(XIN) = 8 MHz, high-speed mode Figure 2.2.15 shows an example of a peripheral circuit, and Figure 2.2.16 shows an example of control procedure. 7540 Group P00/CNTR1 Load Port VAC Fig. 2.2.15 Example of peripheral circuit Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-24 APPLICATION 7540 Group 2.2 Timer A RESET Initialization SEI CLD CLT 10000X002 CPUM (Address 3B16) Wait until f(XIN) oscillation is stabilized (Note 1) CPUM (Address 3B16) 00000X002 CNTR1 interrupt processing routine X: This bit is not used here. Set it to "0" or "1" arbitrary. Set "0" to the CNTR1 interrupt enable bit. (CNTR1 interrupt disabled) Set "0" to the timer A interrupt enable bit. (Timer A interrupt disabled) Set port P00 to the input mode. Set pull-up control register PULL(Address 1616) P00 pull-up control bit 0: Pull-up Off 1: Pull-up On Set timer A mode register 1101 Read timer A (Note 3) RTI Error processing at incorrect period input Timer A interrupt processing routine TAM(Address 1D16) Period measurement mode Rising period measured Rising edge active for CNTR1 interrupt Timer A count stop Error processing Set value to timer A (Note 2) RTI "FF16" "FF16" Timer A (low-order) (Address 1E16) Timer A (high-order) (Address 1F16) Set interrupt edge selection register 1 INTEDGE(Address 3A16) Key-on wakeup disabled Set "0" to the CNTR1 interrupt request bit. Set "0" to the timer A interrupt request bit. Set "1" to the CNTR1 interrupt enable bit. (CNTR1 interrupt enabled) Set "1" to the timer A interrupt enable bit. (Timer A interrupt enabled) Notes 1: For the concrete time, ask the oscillator manufacture. 2: When setting the value to timer A, set in order of low-order byte and high-order byte following. 3: When reading a value of timer A, read in order of high-order byte and low-order byte following. Set timer A mode register TAM(Address 1D16) 0101 Timer A count start CLI CNTR1 interrupt processing Processing Timer A interrupt processing Fig. 2.2.16 Example of control procedure Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-25 APPLICATION 7540 Group 2.2 Timer A 2.2.5 Event counter mode (1) Operation description Timer A counts signals input from the P00/CNTR1 pin. Except for this, the operation in event counter mode is the same as in timer mode. The active edge of CNTR1 pin input signal can be selected from rising or falling by the CNTR1 active edge switch bit. Timer A can stop counting by setting "1" to the timer A count stop bit. Also, when Timer A underflows, the timer A interrupt request bit is set to "1". (2) Event counter mode setting method Figure 2.2.17 and Figure 2.2.18 show the setting method for event counter mode of timer A. Process 1: Disable timer A interrupt and CNTR1 interrupt. b7 b0 0 Interrupt control register 1 (ICON1) [Address 3E16] CNTR1 interrupt disabled b7 b0 0 Interrupt control register 2 (ICON2) [Address 3F16] Timer A interrupt disabled Process 2: Set the CNTR1 pin to the input mode. b7 b0 0 Port P0 direction register (P0D) [Address 0116] Set the P00/CNTR1 pin to the input mode Process 3: Set pull-up control register. b7 b0 Pull-up control register (PULL) [Address 1616] P00/CNTR1 pull-up control bit 0: Pull-up Off 1: Pull-up On Process 4: Set timer A mode register. b7 b0 1 10 Timer A mode register (TAM) [Address 1D16] Event counter mode CNTR1 active edge selected 0: Rising period measured Falling edge active for CNTR1 interrupt 1: Falling period measured Rising edge active for CNTR1 interrupt Timer A count stop Process 5: Set the count value to timer A (Note). * Set the count value to timer A (low-order) Timer A (low-order) (TAL) (Address 1E16) Count value * Set the count value to timer A (high-order) Timer A (high-order) (TAH) (Address 1F16) Count value Note: Write both registers in order of timer X (low-order) and the timer X (high-order) following, certainly. Fig. 2.2.17 Setting method for event counter mode (1) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-26 APPLICATION 7540 Group 2.2 Timer A Process 6: In order to use the CNTR1 pin function of the P00/CNTR1 pin, disable the P00 key-on wakeup function. b7 b0 1 Interrupt edge selection register (INTEDGE) [Address 3A16] Key-on wakeup disabled Process 7: In order not to execute the no requested interrupt processing, set "0" (no requested) to the timer A interrupt request bit and CNTR1 interrupt request bit. b7 b0 0 Interrupt request register 1 (IREQ1) [Address 3C16] No CNTR1 interrupt request issued b7 b0 0 Interrupt request register 2 (IREQ2) [Address 3D16] No timer A interrupt request issued Process 8: When the interrupt is used, set "1" (interrupt enabled) to the timer A interrupt enable bit or CNTR1 interrupt enable bit. b7 b0 1 Interrupt control register 1 (ICON1) [Address 3E16] CNTR1 interrupt enabled b7 b0 1 Interrupt control register 2 (ICON2) [Address 3F16] Timer A interrupt enabled Process 9: Start counting of timer A. b7 b0 0 10 Timer A mode register (TAM) [Address 1D16] Timer A count start Fig. 2.2.18 Setting method for event counter mode (2) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-27 APPLICATION 7540 Group 2.2 Timer A (3) Application example of event counter mode Outline: The frequency of the pulse which is input to the P00/CNTR1 pin ("H" active) is measured by the number of events in a certain period. Specifications: The count source of timer A is input from the P00/CNTR1 pin, and the timer A starts counting the count source. Clock (f(XIN) = 8 MHz) is divided by timer X to detect 1 ms. The frequency of the pulse input to the P00/CNTR1 pin is calculated by the number of events counted within 1 ms. Operation clock: f(XIN) = 8 MHz, high-speed mode Figure 2.2.19 shows an example of measurement method of frequency, and Figure 2.2.20 shows an example of control procedure. 1ms Timer X interrupt request bit P00/CNTR1 pin input Counted by Timer A (Note 1) X times (Note 2) Timer A, Timer X count start Timer X interrupt processing routine * Timer A, Timer X count stop * Timer A read * Timer A, Timer X set again * Timer A, Timer X count restart Notes 1: Counted at falling edge. 2: Frequency of pulse input from P00/CNTR1 pin: X times kHz 1ms Fig. 2.2.19 Example of measurement method of frequency Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-28 APPLICATION 7540 Group 2.2 Timer A RESET Initialization SEI CLD CLT CPUM(Address 3B16) 10000X002 f(XIN) until f(XIN) oscillation is stabilized (Note 1) CPUM(Address 3B16) 00000X002 X: This bit is not used here. Set it to "0" or "1" arbitrary. Timer X interrupt processing routine (1ms interrupt) Set timer A mode register 1 1 10 TAM(Address 1D16) Timer A count stop Set "0" to the CNTR1 interrupt enable bit. (CNTR1 interrupt disabled) Set "0" to the timer A interrupt enable bit. (Timer A interrupt disabled) Set "0" to the timer X interrupt enable bit (Timer X interrupt disabled) Set port P00 to the input mode. Set pull-up control register PULL(Address 1616) P00 pull-up control bit 0: Pull-up Off 1: Pull-up On Set timer A mode register 1110 Set timer X mode register 1 0 0 TXM(Address 2B16) Timer X count stop (Timer A setting value "FFFF16") - (Timer A count value) event in1ms Set value to timer A (Note 2) "FF16" "FF16" Timer A (low-order) (Address 1E16) Timer A (high-order) (Address 1F16) Set value to timer X (Note 3) "0116" "1816" Prescaler X (Address 2C16) Timer X (Address 2D16) TAM(Address 1D16) Event count mode Count at falling edge Timer A count stop Set timer A mode register 0110 TAM(Address 1D16) Timer A count start Set value to timer A (Note 2) "FF16" "FF16" Timer A (low-order) (Address 1E16) Timer A (high-order) (Address 1F16) Set timer X mode register 0 0 0 TXM(Address 2B16) Timer X count start RTI Set timer X mode register 1 0 0 TXM(Address 2B16) Timer mode Timer X count stop Set timer count source set register 0 0 0 TCSS(Address 2E16) Timer X count source: f(XIN)/16 selected Set value to timer X (Note 3) "0116" "F916" Prescaler X (Address 2C16) Timer X (Address 2D16) Notes 1: For the concrete time, ask the oscillator manufacture. 2: When setting the value to timer, set in order of low-order byte and high-order byte following. 3: 1 ms detection = 1/8 MHz 16 (0116 + 1) (F916 + 1) Timer X Prescaler X Timer X division ratio setting value setting value Set interrupt edge selection register 1 INTEDGE(Address 3A16) Key-on wakeup disabled Set timer A mode register 0110 TAM(Address 1D16) Timer A count start Set "0" to the timer X interrupt request bit. Set "1" to the timer X interrupt enable bit. (Timer X interrupt enabled) Set timer X mode register 0 0 0 TXM(Address 2B16) Timer X count start CLI Processing Fig. 2.2.20 Example of control procedure Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-29 APPLICATION 7540 Group 2.2 Timer A 2.2.6 Pulse width HL continuously measurement mode (1) Operation description In the pulse width HL continuously measurement mode, the pulse width ("H" and "L" levels) input to the P00/CNTR1 pin is measured. CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. The count value when trigger input from the CNTR1 pin is accepted is retained until Timer A is read once. Timer A can stop counting by setting "1" to the timer A count stop bit. Also, when Timer A underflows, the timer A interrupt request bit is set to "1". (2) Pulse width HL continuously measurement mode setting method Figure 2.2.21 and Figure 2.2.22 show the setting method for pulse width HL continuously measurement mode of timer A. Process 1: Disable timer A interrupt and CNTR1 interrupt. b7 b0 0 Interrupt control register 1 (ICON1) [Address 3E16] CNT R1 interrupt disabled b7 b0 0 Interrupt control register 2 (ICON2) [Address 3F16] Timer A interrupt disabled Process 2: Set the CNTR1 pin to the input mode. b7 b0 0 Port P0 direction register (P0D) [Address 0116] Set the P00/CNTR1 pin to the input mode Process 3: Set the pull-up control register. b7 b0 Pull-up control register (PULL) [Address 1616] P00/CNTR1 pull-up control bit 0: Pull-up Off 1: Pull-up On Process 4: Set timer A mode register. b7 b0 1 11 Timer A mode register (TAM) [Address 1D16] Pulse width HL continuously measurement mode Timer A count stop Process 5: Set the count value to timer A (Note). * Set the initial value to timer A (low-order) Timer A (low-order) (TAL) (Address 1E16) Initial value * Set the initial value to timer A (high-order) Timer A (high-order) (TAH) (Address 1F16) Initial value Note: Write both registers in order of timer X (low-order) and the timer X (high-order) following, certainly. Fig. 2.2.21 Setting method for pulse width HL continuously measurement mode (1) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-30 APPLICATION 7540 Group 2.2 Timer A Process 6: In order to use the CNTR1 pin function of the P00/CNTR1 pin, disable the P00 key-on wakeup function. b7 b0 1 Interrupt edge selection register (INTEDGE) [Address 3A16] Key-on wakeup disabled Process 7: In order not to execute the no requested interrupt processing, set "0" (no requested) to the timer A interrupt request bit and CNTR1 interrupt request bit (Note). b7 b0 0 Interrupt request register 1 (IREQ1) [Address 3C16] No CNTR1 interrupt request issued b7 b0 0 Interrupt request register 2 (IREQ2) [Address 3D16] No timer A interrupt request issued Note: In the pulse width HL continuously measurement mode, the CNTR1 interrupt request occurs at the rising edge and falling edge of the P00/CNTR1 pin regardless of the value of the P00/CNTR1 active edge switch bit of the timer A mode register. Process 8: When the interrupt is used, set "1" (interrupt enabled) to the timer A interrupt enable bit or CNTR1 interrupt enable bit. b7 b0 1 Interrupt control register 1 (ICON1) [Address 3E16] CNTR1 interrupt enabled b7 b0 1 Interrupt control register 2 (ICON2) [Address 3F16] Timer A interrupt enabled Process 9: Start counting of timer A. b7 b0 0 11 Timer A mode register (TAM) [Address 1D16] Timer A count start Fig. 2.2.22 Setting method for pulse width HL continuously measurement mode (2) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-31 APPLICATION 7540 Group 2.2 Timer A (3) Application example of pulse width HL continuously measurement mode Outline: A telephone ringing (calling) pulse* is detected by using the pulse width HL continuously measurement mode. * Signal which is sent by turning on/off (make/break) the telephone line. Each country has a different standard. In this case, Japanese domestic standard is adopted as an example. Specifications: Whether a telephone call exists or not is judged by measuring a pulse width output from the ringing signal detection circuit. f(XIN)/16 (f(XIN) = 6.4 MHz) is used as the count source, and "H" and "L" pulse width of the ringing pulse are measured by using the pulse width HL continuously measurement mode. When the following conditions are satisfied, it is recognized as a normal value. When the following conditions are not satisfied, it is recognized as an unusual value. 200 ms "H" pulse width of ringing pulse < 1.2 s 600 ms "L" pulse width of ringing pulse < 2.2 s 1.0 s one period ("H" pulse width + "L" pulse width) < 3.0 s Operation clock: f(XIN) = 6.4 MHz, high-speed mode Figure 2.2.23 shows an example of a peripheral circuit, and Figure 2.2.24 shows an operation timing when a ringing pulse is input. Figures 2.2.25 and 2.2.26 show an example of control procedure. 7540 Group Ringing pulse detection circuit P00/CNTR1 Telephone line Fig. 2.2.23 Example of peripheral circuit q When a normal-range ringing pulse is input Ringing duration (200 ms to 1.2 s) No ringing duration (600 ms to 2.2 s) (1.0 s to 3.0 s) Input signal to P00/CNTR1 pin Timer A value Timer A interrupt request 4 to 23 interrupts occur Reload Reload 12 to 43 interrupts occur 1 period 20 to 59 interrupts occur CNTR1 interrupt request "H" width measurement end "L" width measurement end Fig. 2.2.24 Operation timing when ringing pulse is input Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-32 APPLICATION 7540 Group 2.2 Timer A RESET Initialization SEI CLD CLT 10000X002 CPUM(Address 3B16) Wait until f(XIN) oscillation is stabilized (Note 1) 00000X002 CPUM(Address 3B16) X: This bit is not used here. Set it to "0" or "1" arbitrary. Set "0" to the timer A interrupt enable bit. (Timer A interrupt disabled) Set "0" to the CNTR1 interrupt enable bit. (CNTR1 interrupt disabled) Set port P00 to the input mode. Set pull-up control register PULL(Address 1616) P00 pull-up control bit 0: Pull-up Off 1: Pull-up On Set timer A mode register 1 11 TAM(Address 1D16) Pulse width HL continuously measurement mode Timer A count stop Set value to timer A (Notes 2, 3) "1F16" "4E16" Timer A (low-order) (Address 1E16) Timer A (high-order) (Address 1F16) Set interrupt edge selection register 1 INTEDGE(Address 3A16) Key-on wakeup disabled Set "0" to the CNTR1 interrupt request bit. Set "0" to the timer A interrupt request bit. Set "1" to the CNTR1 interrupt enable bit. (CNTR1 interrupt enabled) Set "1" to the timer A interrupt enable bit. (Timer A interrupt enabled) Set timer A mode register 0 11 TAM(Address 1D16) Timer A count start Notes 1: For the concrete time, ask the oscillator manufacture. 2: When setting the value to timer A, set in order of low-order byte and high-order byte following. 3: 50 ms = 1/6.4 MHz 16 (4E1F16 + 1) Timer A division ratio (fixed) Timer A setting value CLI Main processing CNTR1 interrupt occurs at rising edge and falling edge of waveform which is input to P00/CNTR1 pin Timer A interrupt occurs at timer A underflow (at every 50 ms) N A ringing pulse exists ? (Ringer flag = "1"?) Y Processing when a ringing pulse exists CNTR1 interrupt processing Timer A interrupt processing Main processing Fig. 2.2.25 Example of control procedure (1) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-33 APPLICATION 7540 Group 2.2 Timer A CNTR1 interrupt processing routine L e v e l o f P 00/C N T R 1 is c h e c k e d , a n d w h ic h d u ra t io n m e a s u rin g is fin is h e d is ju d g e d . When P00/CNTR1 = "0", "H" duration measuring is finished. When P00/CNTR1 = "1", "L" duration measuring is finished. N T h e n u m b e r o f u n d e rflo w is w ith in th e ra n g e ? ("4 " o r m o re a n d le s s th a n "2 3 ") Y Set "1" to the "H" width decision flag. T h e n u m b e r o f u n d e rflo w is w ith in th e ra n g e ? ("1 2 " o r m o re a n d le s s t h a n "4 3 ") Y Set "1" to the "L" width decision flag. N T h e n u m b e r o f a p e rio d 's u n d e rflo w is w ith in th e ra n g e ? ("2 0 " o r m o re a n d le s s t h a n "5 9 ") N Y When judging that a ringing pulse exists as a result of several period measurement, set "1" to the ringing flag. * Error processing Set "0" to the "H" width decision flag and the "L" width decision flag. Set "1" to the unusual value detection flag * Error processing RTI Timer A interrupt processing routine Count the number of underflows RTI Fig. 2.2.26 Example of control procedure (2) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-34 APPLICATION 7540 Group 2.2 Timer A 2.2.7 Notes on timer A Notes on using timer A are described below. (1) Common to all modes When reading timer A (high-order) (TAH) and timer A (low-order) (TAL), the contents of timer A is read out. Read both registers in order of TAH and TAL following, certainly. TAH and TAL keep the values until they are read out. Also, do not write to them during read. In this case, unexpected operation may occur. When writing data to TAL and TAH when timer A is operating or stopped, the data are set to timer A and timer A latch simultaneously. Write both registers in order of TAL and TAH following, certainly. Also, do not read them during write. In this case, unexpected operation may occur. (2) Period measurement mode, event counter mode, and pulse width HL continuously measurement mode In order to use CNTR1 pin, set "0" to bit 0 of the port P0 direction register (input mode). In order to use CNTR1 pin, set "1" to bit 7 of the interrupt edge selection register to disable the P00 key-on wakeup function. CNTR1 interrupt active edge depends on the CNTR1 active edge switch bit. When this bit is "0", the CNTR1 interrupt request bit is set to "1" at the falling edge of the CNTR1 pin input signal. When this bit is "1", the CNTR1 interrupt request bit is set to "1" at the rising edge of the CNTR1 pin input signal. However, in the pulse width HL continuously measurement mode, CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR1 active edge switch bit. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-35 APPLICATION 7540 Group 2.3 Timer 1 2.3 Timer 1 This paragraph explains the registers setting method and the notes relevant to the timer 1. 2.3.1 Memory map 002816 002916 Prescaler 1 (PRE1) Timer 1 (T1) 003816 MISRG 003D16 Interrupt request register 2 (IREQ2) 003F16 Interrupt control register 2 (ICON2) Fig. 2.3.1 Memory map of registers relevant to timer 1 2.3.2 Relevant registers Prescaler 1 b7 b6 b5 b4 b3 b2 b1 b0 Prescaler 1 (PRE1) [Address : 2816] B Function At reset RW 0 *Set a count value of prescaler 1. *The value set in this register is written to both prescaler 1 and the prescaler 1 latch at the same time. *When this register is read out, the count value of the prescaler 1 2 is read out. 1 1 1 1 1 1 1 1 1 3 4 5 6 7 Fig. 2.3.2 Structure of Prescaler 1 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-36 APPLICATION 7540 Group 2.3 Timer 1 Timer 1 b7 b6 b5 b4 b3 b2 b1 b0 Timer 1 (T1) [Address : 29 16] B Function At reset RW 0 *Set a count value of timer 1. *The value set in this register is written to both timer 1 and timer 1 1 latch at the same time. *When this register is read out, the timer 1's count value is read 2 out. 1 0 0 0 0 0 0 0 3 4 5 6 7 Fig. 2.3.3 Structure of Timer 1 MISRG b7 b6 b5 b4 b3 b2 b1 b0 MISRG [Address : 3816] B Name set bit after release of the STP instruction Function 0 : Set "0116" in timer 1, and "FF16" in prescaler 1 automatically 1 : Not set automatically 1 : Detection function active At reset RW 0 Oscillation stabilization time 0 1 Ceramic or RC oscillation stop 0 : Detection function inactive detection function active bit 2 These are reserved bits. Do not write "1" to these bits. 0 0 0 3 4 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 0 0 0 5 6 7 Oscillation stop detection status bit 0 : Oscillation stop not detected 1 : Oscillation stop detected (Note) Note: "0" at normal reset "1" at reset by detecting the oscillation stop Fig. 2.3.4 Structure of MISRG Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-37 APPLICATION 7540 Group 2.3 Timer 1 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2) [Address : 3D 16] B Name Function 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset RW 0 Timer Y interrupt request bit 1 Timer Z interrupt request bit 2 Timer A interrupt request bit 3 Serial I/O2 interrupt request bit 4 AD converter interrupt request bit 0 0 0 0 0 0 0 0 5 Timer 1 interrupt request bit 6 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 7 : These bits can be cleared to "0" by program, but cannot be set to "1". Fig. 2.3.5 Structure of Interrupt request register 2 Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 2 (ICON2) [Address : 3F 16] B Name Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset RW 0 Timer Y interrupt enable bit 1 Timer Z interrupt enable bit 0 0 0 0 0 0 0 0 2 Timer A interrupt enable bit 3 Serial I/O2 interrupt enable bit 4 AD conversion interrupt enable bit 5 Timer 1 interrupt enable bit 6 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 7 Fig. 2.3.6 Structure of Interrupt control register 2 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-38 APPLICATION 7540 Group 2.3 Timer 1 2.3.3 Timer 1 operation description Timer 1 always operates in the timer mode. Prescaler 1 counts the selected count source. Each time the count clock is input, the contents of Prescaler 1 is decremented by 1. When the contents of Prescaler 1 reach "0016", an underflow occurs at the next count clock, and the prescaler 1 latch is reloaded into Prescaler 1 and count continues. The division ratio of Prescaler 1 is 1/ (n+1) provided that the value of Prescaler 1 is n. The contents of Timer 1 is decremented by 1 each time the underflow signal of Prescaler 1 is input. When the contents of Timer 1 reach "0016", an underflow occurs at the next count clock, and the timer 1 latch is reloaded into Timer 1 and count continues. The division ratio of Timer 1 is 1/(m+1) provided that the value of Timer 1 is m. Accordingly, the division ratio of Prescaler 1 and Timer 1 is provided as follows that the value of Prescaler 1 is n and the value of Timer 1 is m. Division ratio = 1 (n+1) (m+1) Timer 1 cannot stop counting by software. Also, when timer 1 underflows, the timer 1 interrupt request bit is set to "1". 2.3.4 Notes on timer 1 Note on using timer 1 is described below. (1) Notes on set of the oscillation stabilizing time Timer 1 can be used to set the oscillation stabilizing time after release of the STP instruction. The oscillation stabilizing time after release of STP instruction can be selected from "set automatically"/ "not set automatically" by the oscillation stabilizing time set bit after release of the STP instruction of MISRG. When "0" is set to this bit, "0116" is set to timer 1 and "FF16" is set to prescaler 1 automatically. When "1" is set to this bit, nothing is set to timer 1 and prescaler 1. Therefore, set the wait time according to the oscillation stabilizing time of the oscillation. Also, when timer 1 is used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-39 APPLICATION 7540 Group 2.4 Timer X 2.4 Timer X This paragraph explains the registers setting method and the notes relevant to the timer X. 2.4.1 Memory map 000116 Port P0 direction register (P0D) Port P1 direction register (P1D) 000316 002B16 002C16 002D16 002E16 Timer X mode register (TXM) Prescaler X (PREX) Timer X (TX) Timer count source set register (TCSS) 003C16 Interrupt request register 1 (IREQ1) 003E16 Interrupt control register 1 (ICON1) Fig. 2.4.1 Memory map of registers relevant to timer X Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-40 APPLICATION 7540 Group 2.4 Timer X 2.4.2 Relevant registers Port P0 direction register b7 b6 b5 b4 b3 b2 b1 b0 Port P0 direction register (P0D) [Address : 01 16] B Name Function 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode At reset RW 0 Port P0 direction register 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 Fig. 2.4.2 Structure of Port P0 direction register Port P1 direction register b7 b6 b5 b4 b3 b2 b1 b0 Port P1 direction register (P1D) [Address : 03 16] B Name Function 0 : Port P10 input mode 1 : Port P10 output mode 0 : Port P11 input mode 1 : Port P11 output mode 0 : Port P12 input mode 1 : Port P12 output mode 0 : Port P13 input mode 1 : Port P13 output mode 0 : Port P14 input mode 1 : Port P14 output mode At reset RW 0 Port P1 direction register 1 2 3 4 0 0 0 0 0 ? ? ? 5 Nothing is allocated for these bits. When these bits are read out, the values are undefined. 6 7 Fig. 2.4.3 Structure of Port P1 direction register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-41 APPLICATION 7540 Group 2.4 Timer X Timer X mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register (TXM) [Address : 2B 16] B Name b1 b0 Function 0 0 1 1 0 : Timer mode 1 : Pulse output mode 0 : Event counter mode 1 : Pulse width measurement mode At reset RW 0 Timer X operating mode bits 0 1 2 CNTR0 active edge switch bit 0 0 The function depends on the operating mode. (Refer to Table 2.4.1) 0 : Count start 1 : Count stop 0 : Output invalid (I/O port) 1 : Output valid (Inverted CNTR 0 output) 3 Timer X count stop bit 4 P03/TXOUT output valid bit 0 0 5 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 0 0 0 6 7 Fig. 2.4.4 Structure of Timer X mode register Table 2.4.1 CNTR0 active edge switch bit function Timer X operating modes Timer mode CNTR0 active edge switch bit (bit 2 of address 2B16) contents "0" CNTR0 interrupt request occurrence: Falling edge ; No influence to timer count "1" CNTR0 interrupt request occurrence: Rising edge ; No influence to timer count Pulse output mode "0" Pulse output start: Beginning at "H" level CNTR0 interrupt request occurrence: Falling edge "1" Pulse output start: Beginning at "L" level CNTR0 interrupt request occurrence: Rising edge Event counter mode "0" Timer X: Rising edge count CNTR0 interrupt request occurrence: Falling edge "1" Timer X: Falling edge count CNTR0 interrupt request occurrence: Rising edge Pulse width measurement mode "0" Timer X: "H" level width measurement CNTR0 interrupt request occurrence: Falling edge "1" Timer X: "L" level width measurement CNTR0 interrupt request occurrence: Rising edge Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-42 APPLICATION 7540 Group 2.4 Timer X Prescaler X b7 b6 b5 b4 b3 b2 b1 b0 Prescaler X (PREX) [Address : 2C 16] B Function At reset RW 0 *Set a count value of prescaler X. *The value set in this register is written to both prescaler X and the prescaler X latch at the same time. *When this register is read out, the count value of the prescaler X 2 is read out. 1 1 1 1 1 1 1 1 1 3 4 5 6 7 Fig. 2.4.5 Structure of Prescaler X Timer X b7 b6 b5 b4 b3 b2 b1 b0 Timer X (TX) [Address : 2D 16] B Function At reset RW 0 *Set a count value of timer X. *The value set in this register is written to both timer X and timer X 1 latch at the same time. *When this register is read out, the timer X's count value is read 2 out. 1 1 1 1 1 1 1 1 3 4 5 6 7 Fig. 2.4.6 Structure of Timer X Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-43 APPLICATION 7540 Group 2.4 Timer X Timer count source set register b7 b6 b5 b4 b3 b2 b1 b0 0 Timer count source set register (TCSS) [Address : 2E16] B Name b1 b0 Function 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : f(XIN) (Note 1) 1 1 : Not available b3 b2 At reset RW 0 Timer X count source selection bits 1 2 Timer Y count source selection bits 0 0 0 0 0 0 0 0 3 4 Timer Z count source selection bits 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : On-chip oscillator output (Note 2) 1 1 : Not available b5 b4 5 6 Fix this bit to "0". 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : Timer Y underflow 1 1 : Not available 7 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". Notes 1: f(XIN) can be used as timer X count source only when using a ceramic oscillator or on-chip oscillator. Do not use it at RC oscillation. 2: System operates using an on-chip oscillator as a count source by setting the on-chip oscillator to oscillation enabled by bit 3 of CPUM. Fig. 2.4.7 Structure of Timer count source set register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-44 APPLICATION 7540 Group 2.4 Timer X Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address : 3C 16] B Name Function 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset RW 0 Serial I/O1 receive interrupt request bit 1 Serial I/O1 transmit interrupt request bit 0 0 0 0 0 0 0 0 2 INT0 interrupt request bit 3 INT1 interrupt request bit 4 Key-on wake up interrupt request bit 5 CNTR0 interrupt request bit 6 CNTR1 interrupt request bit 7 Timer X interrupt request bit : These bits can be cleared to "0" by program, but cannot be set to "1". Fig. 2.4.8 Structure of Interrupt request register 1 Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address : 3E 16] B Name Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset RW 0 Serial I/O1 receive interrupt enable bit 1 Serial I/O1 transmit interrupt enable bit 2 INT0 interrupt enable bit 3 INT1 interrupt enable bit 4 Key-on wake up interrupt enable bit 0 0 0 0 0 0 0 0 5 CNTR0 interrupt enable bit 6 CNTR1 interrupt enable bit 7 Timer X interrupt enable bit Fig. 2.4.9 Structure of Interrupt control register 1 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-45 APPLICATION 7540 Group 2.4 Timer X 2.4.3 Timer mode (1) Operation description Prescaler X counts the selected count source by the timer X count source selection bits. Each time the count clock is input, the contents of Prescaler X is decremented by 1. When the contents of Prescaler X reach "0016", an underflow occurs at the next count clock, and the prescaler X latch is reloaded into Prescaler X and count continues. The division ratio of Prescaler X is 1/(n+1) provided that the value of Prescaler X is n. The contents of Timer X is decremented by 1 each time the underflow signal of Prescaler X is input. When the contents of Timer X reach "0016", an underflow occurs at the next count clock, and the timer X latch is reloaded into Timer X and count continues. The division ratio of Timer X is 1/(m+1) provided that the value of Timer X is m. Accordingly, the division ratio of Prescaler X and Timer X is provided as follows that the value of Prescaler X is n and the value of Timer X is m. 1 Division ratio = (n+1) (m+1) Timer X can stop counting by setting "1" to the timer X count stop bit. Also, when Timer X underflows, the timer X interrupt request bit is set to "1". (2) Timer mode setting method Figure 2.4.10 shows the setting method for timer mode of timer X. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-46 APPLICATION 7540 Group 2.4 Timer X Process 1: Disable timer X interrupt. b7 b0 0 Interrupt control register 1 (ICON1) [Address 3E16] Timer X interrupt disabled Process 2: Set timer X mode register. b7 b0 1 00 Timer X mode register (TXM) [Address 2B16] Timer mode Timer X count stop Process 3: Set timer count source set register. b7 b0 0 Timer count source set register (TCSS) [Address 2E16] Timer X count source selection bits b1 b0 0 0 1 1 0 : f(XIN)/16 1 : f(XIN)/2 0 : f(XIN) (Note) 1 : Not available Note: f(XIN) can be used only when a ceramic resonator or an on-chip oscillator is used. Do not use f(XIN) at RC oscillation. Process 4: Set the count value to timer X. * Set the count value to prescaler X and timer X Prescaler X (PREX) (Address 2C16) Count value Timer X (TX) (Address 2D16) Count value Process 5: In order not to execute the no requested interrupt processing, set "0" (no requested) to the timer X interrupt request bit. b7 b0 0 Interrupt request register 1 (IREQ1) [Address 3C16] No timer X interrupt request issued Process 6: When timer X interrupt is used, set "1" (interrupt enabled) to the timer X interrupt enable bit. b7 b0 1 Interrupt control register 1 (ICON1) [Address 3E16] Timer X interrupt enabled Process 7: Start counting of timer X. b7 b0 0 00 Timer X mode register (TXM) [Address 2B16] Timer X count start Fig. 2.4.10 Setting method for timer mode Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-47 APPLICATION 7540 Group 2.4 Timer X (3) Application example of timer mode Outline: The input clock is divided by the timer so that the clock is counted up every 250 ms intervals. Specifications: *The f(XIN) = 4.19 MHz (2 22 Hz) is divided by timer X. *The clock is counted up in the timer X interrupt processing routine (timer X interrupt occurs every 250 ms). * Operation clock: f(XIN) = 4.19 MHz, high-speed mode Figure 2.4.11 shows the connection of timer and setting of division ratio and Figure 2.4.12 shows an example of control procedure. Timer X count source selection bits f(XIN) = 4.19 MHz 1/16 Prescaler X 1/256 Timer X 1/256 Timer X interrupt Divided by 4 by software request bit 0 or 1 250 ms 1/4 1s 0: No interrupt request 1: Interrupt request Fig. 2.4.11 Connection of timer and setting of division ratio Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-48 APPLICATION 7540 Group 2.4 Timer X RESET Initialization SEI CLD CLT CPUM(Address 3B16) 10000X002 Wait until f(XIN) oscillation is stabilized (Note 1) 00000X002 CPUM(Address 3B16) X: This bit is not used here. Set it to "0" or "1" arbitrary. Processing of clock setting Set "0" to the timer X interrupt enable bit. (Timer X interrupt disabled) Set "0" to the timer X interrupt enable bit. (Timer X interrupt disabled) Set timer X mode register 1 0 1 00 Clock setting Set timer X mode register 0 1 00 TXM(Address 2B16) Timer mode Timer X count stop TXM(Address 2B16) Timer X count stop Set value to timer X (Note 2) "FF16" "FF16" Prescaler X (Address 2C16) Timer X (Address 2D16) Set timer count source set register 10 00 TCSS(Address 2E16) Timer X count source: f(XIN)/16 selected Set "0" to the timer X interrupt request bit. Set value to timer X (Note 2) "FF16" "FF16" Prescaler X (Address 2C16) Timer X (Address 2D16) Set "1" to the timer X interrupt enable bit. (Timer X interrupt enabled) Set timer X mode register 1 0 0 0 0 TXM(Address 2B16) Timer X count start Set "0" to the timer X interrupt request bit. Set "1" to the timer X interrupt enable bit. (Timer X interrupt enabled) Set timer X mode register 1 0 0 0 0 TXM(Address 2B16) Timer X count start RTS CLI Notes 1: For the concrete time, ask the oscillator manufacture. 2: About 250 ms = 1/4.19 MHz 16 (FF16 + 1) (FF16 + 1) Timer X Prescaler X Timer X division ratio setting value setting value Timer X interrupt processing routine Processing Y Clock is stopped? Setting clock is required? Y Clock count up (1/4 s to year) Processing of setting clock RTI N N Fig. 2.4.12 Example of control procedure Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-49 APPLICATION 7540 Group 2.4 Timer X 2.4.4 Pulse output mode (1) Operation description In the pulse output mode, the waveform whose polarity is inverted each time timer X underflows is output from the P14/CNTR0 pin. The output level of CNTR0 pin can be selected by the CNTR0 active edge switch bit. When the CNTR0 active edge switch bit is "0", the output of CNTR0 pin is started at "H" level. When this bit is "1", the output is started at "L" level. Also, the inverted waveform of pulse output from CNTR0 pin can be output from TXOUT pin by setting "1" to the P03/TXOUT output valid bit. When using a timer in this mode, set the port P14 and P03 direction registers to output mode. Timer X can stop counting by setting "1" to the timer X count stop bit. Also, when Timer X underflows, the timer X interrupt request bit is set to "1". (2) Pulse output mode setting method Figure 2.4.13 and Figure 2.4.14 show the setting method for pulse output mode of timer X. Process 1: Disable timer X interrupt. b7 b0 0 Interrupt control register 1 (ICON1) [Address 3E16] Timer X interrupt disabled Process 2: Set timer X mode register. b7 b0 1 01 Timer X mode register (TXM) [Address 2B16] Pulse output mode CNTR0 active edge switch 0: Output is started at "H" level 1: Output is started at "L" level Timer X count stop P03/TXOUT output 0: Output invalid (I/O port) 1: Output valid (inverted CNTR0 output) Process 3: Set the CNTR0 pin to the output mode. b7 b0 1 Port P1 direction register (P1D) [Address 0316] Set the P14/CNTR0 pin to the output mode Process 4: Set the TXOUT pin as the output mode when TXOUT output is valid. b7 b0 1 Port P0 direction register (P0D) [Address 0116] Set the P03/TXOUT pin to the output mode Fig. 2.4.13 Setting method for pulse output mode (1) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-50 APPLICATION 7540 Group 2.4 Timer X Process 5: Set timer count source set register. b7 b0 0 Timer count source set register (TCSS) [Address 2E16] Timer X count source selection bits b1 b0 0 0 1 1 0 : f(XIN)/16 1 : f(XIN)/2 0 : f(XIN) (No te) 1 : Not available Note: f(XIN) can be used only when a ceramic resonator or an on-chip oscillator is used. Do not use f(XIN) at RC oscillation. Process 6: Set the count value to timer X. * Set the count value to prescaler X and timer X Prescaler X (PREX) (Address 2C16) Count value Timer X (TX) (Address 2D16) Count value Process 7: In order not to execute the no requested interrupt processing, set "0" (no requested) to the timer X interrupt request bit. b7 b0 0 Interrupt request register 1 (IREQ1) [Address 3C16] No timer X interrupt request issued Process 8: When the interrupt is used, set "1" (interrupt enabled) to the timer X interrupt enable bit. b7 b0 1 Interrupt control register 1 (ICON1) [Address 3E16] Timer X interrupt enabled Process 9: Start counting of timer X. b7 b0 0 01 Timer X mode register (TXM) [Address 2B16] Timer X count start Fig. 2.4.14 Setting method for pulse output mode (2) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-51 APPLICATION 7540 Group 2.4 Timer X (3) Application example of pulse output mode Outline: The pulse output mode of timer X is used for a piezoelectric buzzer output. Specifications: The rectangular waveform which is clock f(XIN) = 4 MHz divided up to 4 kHZ is output from the P14/CNTR0 pin. The level of the P14/CNTR0 pin is fixed to "H" while a piezoelectric buzzer output is stopped. Operation clock: f(XIN) = 4 MHz, double-speed mode Figure 2.4.15 shows an example of a peripheral circuit, Figure 2.4.16 shows the connection of timer and setting of the division ratio, and Figure 2.4.17 shows an example of control procedure. The "H" level is output while a piezoelectric buzzer output is stopped. CNTR0 output 7540 Group P14/CNTR0 125 s 125 s Set division ratio so that the underflow output period of timer X will become 125 s. PiPiPi..... Fig. 2.4.15 Example of peripheral circuit Timer X count source selection bit f(XIN) = 4MHz 1/2 Prescaler X 1/2 Timer X Fixed 1/125 1/2 CNTR0 pin output 4 kHz Fig. 2.4.16 Connection of timer and setting of division ratio Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-52 APPLICATION 7540 Group 2.4 Timer X RESET Initialization SEI CLD CLT 10000X002 CPUM(Address 3B16) Wait until f(XIN) oscillation is stabilized (Note 1) CPUM(Address 3B16) 11000X002 X: This bit is not used here. Set it to "0" or "1" arbitrary. Set "0" to the CNTR0 interrupt enable bit. (CNTR0 interrupt disabled) Set "0" to the timer X interrupt enable bit. (Timer X interrupt disabled) Set port P14 to the output mode. Set "1" to port P14. ("H" output) Set timer X mode register 1 0 1001 TXM(Address 2B16) Pulse output mode Output is started at "H" level Timer X count stop Set timer count source set register 10 01 TCSS(Address 2E16) Timer X count source: f(XIN)/2 selected Set value to timer X (Notes 2, 3) "0116" "7C16" Prescaler X (Address 2C16) Timer X (Address 2D16) Notes 1: For the concrete time, ask the oscillator manufacture. 2: 125 s = 1/4 MHz 2 (0116 + 1) (7C16 + 1) Timer X division ratio Prescaler X setting value Timer X setting value 3: The output level of P14/CNTR0 pin is initialized by writing to timer X. CLI Processing Buzzer output processing Buzzer output is requested? Y Timer X count is stopped? Y Set timer X mode register 1 0 0001 N Timer X count is operating? N Y Set timer X mode register 1 0 10 01 N TXM(Address 2B16) Timer X count stop TXM(Address 2B16) Timer X count start Set value to timer X (Note 3) "7C16" Timer X (Address 2D16) Processing Fig. 2.4.17 Example of control procedure Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-53 APPLICATION 7540 Group 2.4 Timer X 2.4.5 Event counter mode (1) Operation description The timer X counts signals input from the P14/CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. The active edge of CNTR0 pin input signal can be selected from rising or falling by the CNTR0 active edge switch bit. Timer X can stop counting by setting "1" to the timer X count stop bit. Also, when Timer X underflows, the timer X interrupt request bit is set to "1". (2) Event counter mode setting method Figure 2.4.18 and Figure 2.4.19 show the setting method for event counter mode of timer X. Process 1: Disable timer X interrupt and CNTR0 interrupt. b7 b0 0 0 Interrupt control register 1 (ICON1) [Address 3E16] CNT R0 interrupt disabled Timer X interrupt disabled Process 2: Set the CNTR0 pin to the input mode. b7 b0 0 Port P1 direction register (P1D) [Address 0316] Set the P14/CNTR0 pin to the input mode Process 3: Set timer X mode register. b7 b0 1 10 Timer X mode register (TXM) [Address 2B16] Event counter mode CNTR0 active edge switch 0: Count at rising edge CNTR0 interrupt request occurs at falling edge 1: Count at falling edge CNTR0 interrupt request occurs at rising edge Timer X count stop Process 4: Set timer count source set register. b7 b0 0 Timer count source set register (TCSS) [Address 2E16] Timer X count source selection bits b1 b0 0 0 1 1 0 : f(XIN)/16 1 : f(XIN)/2 0 : f(XIN) (Note) 1 : Not available Note: f(XIN) can be used only when a ceramic oscillator or an on-chip oscillator is used. Do not use f(XIN) at RC oscillation. Fig. 2.4.18 Setting method for event counter mode (1) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-54 APPLICATION 7540 Group 2.4 Timer X Process 5: Set the count value to timer X. * Set the count value to prescaler X and timer X Prescaler X (PREX) (Address 2C16) Count value Timer X (TX) (Address 2D16) Count value Process 6: In order not to execute the no requested interrupt processing, set "0" (no requested) to the timer X interrupt request bit and CNTR1 interrupt request bit. b7 b0 0 0 Interrupt request register 1 (IREQ1) [Address 3C16] No CNTR0 interrupt request is issued No timer X interrupt request issued Process 7: When the interrupt is used, set "1" (interrupt enabled) to the timer X interrupt enable bit. b7 b0 1 1 Interrupt control register 1 (ICON1) [Address 3E16] CNT R0 interrupt enabled Timer X interrupt enabled Process 8: Start counting of timer X. b7 b0 0 10 Timer X mode register (TXM) [Address 2B16] Timer X count start Fig. 2.4.19 Setting method for event counter mode (2) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-55 APPLICATION 7540 Group 2.4 Timer X (3) Application example of event counter mode Outline: Pulses generated corresponding to the water flow rate are counted for a fixed period (100 ms), and the water flow rate during this period is calculated. Specifications: Pulses generated corresponding to the water flow rate are input to the P14/CNTR0 pin and counted using timer X. The contents of timer X are read in the timer Y interrupt processing routine generated after 100 ms from the start of counting pulses, and the water flow rate during 100 ms is calculated. Operation clock: f(XIN) = 8 MHz, high-speed mode Figure 2.4.20 shows an example of peripheral circuit, Figure 2.4.21 shows the method of measuring water flow rate, and Figure 2.4.21 shows an example of control procedure. 7540 Group Water flow rate sensor Water flow P14/CNTR0 Blades rotate in proportion to water flow and generate pulses. The faster the water flow, the shorter the pulse period. Fig. 2.4.20 Example of peripheral circuit 100 ms Timer Y interrupt request bit CNTR0 pin input Timer X counting (Note) Timer X, timer Y start counting. Timer Y interrupt processing routine * Timer X, timer Y stop counting. * Timer X is read out. Note: Counting rising edges. * Flow rate during 100 ms = (FF16-read value of timer X) flow rate per pulse Fig. 2.4.21 Method of measuring water flow rate Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-56 APPLICATION 7540 Group 2.4 Timer X Flow rate measuring routine Set "0" to the CNTR0 interrupt enable bit. (CNTR0 interrupt disabled) Set "0" to the timer X interrupt enable bit. (Timer X interrupt disabled) Set "0" to the timer Y interrupt enable bit. (Timer Y interrupt disabled) 1 0 Timer Y interrupt processing routine Set timer X mode register Set port P14 to the input mode. Set timer X mode register 1 0 11 10 1 1 1 0 TXM(Address 2B16) Timer X count stop TXM(Address 2B16) Event counter mode Count at falling edge Timer X count stop Set timer Y, Z mode register 10 0 Set timer Y, Z mode register 10 0 TYZM(Address 2016) Timer Y count stop (Prescaler X setting value "FF16" Timer X setting value "FF16") - (Prescaler X count value, Timer X count value) The numbeer of event within 100 ms RTI TYZM(Address 2016) Timer mode Writing to latch and timer simultaneously Timer Y count stop Set timer count source set register 10 00 TCSS(Address 2E16) Timer Y count source: f(XIN)/16 selected Note : 100 ms = 1/8 MHz 16 (C716 + 1) (F916 + 1) Timer Y division ratio Prescaler Y setting value Timer Y primary setting value Set value to timer X "FF16" "FF16" Prescaler X (Address 2C16) Timer X (Address 2D16) Set value to timer Y (Note) "C716" "F916" Prescaler Y (Address 2116) Timer Y primary (Address 2316) Set "0" to the timer Y interrupt request bit. Set "1" to the timer Y interrupt enable bit. (Timer Y interrupt enabled) Set timer X mode register 1 0 0 110 TXM(Address 2B16) Timer X count start Set timer Y, Z mode register 00 0 TYZM(Address 2016) Timer Y count start END Fig. 2.4.22 Example of control procedure Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-57 APPLICATION 7540 Group 2.4 Timer X 2.4.6 Pulse width measurement mode (1) Operation description In the pulse width measurement mode, the pulse width of the signal input to P14/CNTR0 pin is measured. The operation of Timer X can be controlled by the level of the signal input from the CNTR0 pin. When the CNTR0 active edge switch bit is "0", the signal selected by the timer X count source selection bit is counted while the input signal level of CNTR0 pin is "H". The count is stopped while the pin is "L". Also, when the CNTR0 active edge switch bit is "1", the signal selected by the timer X count source selection bit is counted while the input signal level of CNTR0 pin is "L". The count is stopped while the pin is "H". Timer X can stop counting by setting "1" to the timer X count stop bit. Also, when Timer X underflows, the timer X interrupt request bit is set to "1". (2) Pulse width HL continuously measurement mode setting method Figure 2.4.23 and Figure 2.4.24 show the setting method for pulse width measurement mode of timer X. Process 1: Disable timer X interrupt and CNTR0 interrupt. b7 b0 0 0 Interrupt control register 1 (ICON1) [Address 3E16] CNTR0 interrupt disabled Timer X interrupt disabled Process 2: Set the CNTR0 pin to the input mode. b7 b0 0 Port P1 direction register (P1D) [Address 0316] Set the P14/CNTR0 pin to the input mode Process 3: Set timer X mode register. b7 b0 1 11 Timer X mode register (TXM) [Address 2B16] Pulse width measurement mode CNT R0 active edge switch 0: "H" level width measurement 1: "L" level width measurement Timer X count stop Process 4: Set timer X count source. b7 b0 0 Timer count source set register (TCSS) [Address 2E16] Timer X count source selection bits b1 b0 0 0 1 1 0 : f(XIN)/16 1 : f(XIN)/2 0 : f(XIN) (Note) 1 : Not available Note: f(XIN) can be used only when a ceramic resonator or an on-chip oscillator is used. Do not use f(XIN) at RC oscillation. Fig. 2.4.23 Setting method for pulse width measurement mode (1) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-58 APPLICATION 7540 Group 2.4 Timer X Process 5: Set the count value to timer X. * Set the initial value to prescaler X and timer X Prescaler X (PREX) (Address 2C16) Initial value Timer X (TX) (Address 2D16) Initial value Process 6: In order not to execute the no requested interrupt processing, set "0" (no requested) to the timer X interrupt request bit and CNTR0 interrupt request bit. b7 b0 0 0 Interrupt request register 1 (IREQ1) [Address 3C16] No CNTR0 interrupt request is issued No timer X interrupt request issued Process 7: When the interrupt is used, set "1" (interrupt enabled) to the timer X interrupt enable bit. b7 b0 1 1 Interrupt control register 1 (ICON1) [Address 3E16] CNTR0 interrupt enabled Timer X interrupt enabled Process 8: Start counting of timer X. b7 b0 0 11 Timer X mode register (TXM) [Address 2B16] Timer X count start Fig. 2.4.24 Setting method for pulse width measurement mode (2) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-59 APPLICATION 7540 Group 2.4 Timer X (3) Application example of pulse width measurement mode Outline: "H" level width of pulse input to P14/CNTR0 pin is counted. Specifications: The "H" level width of a FG pulse input to the P14/CNTR0 pin is counted. An underflow is detected by the timer X interrupt. The completion of "H" level of input pulse is detected by the CNTR0 interrupt. Operation clock: f(XIN) = 4.19 MHz, high-speed mode Example: When f(XIN) = 4.19 MHz, the count source becomes 3.8 s divided by 16. Measurement can be made up to 250 ms in the range of "FFFF16" to "000016". Figure 2.4.25 shows a connection of the timer and setting of the division ratio. Figure 2.4.26 shows an example of control procedure. Timer X count source selection bit Prescaler X f(XIN) = 4.19MHz 1/16 1/256 Timer X 1/256 Timer X interrupt request bit 0 or 1 250 m s 0: No interrupt request 1: Interrupt request Fig. 2.4.25 Connection of timer and setting of division ratio Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-60 APPLICATION 7540 Group 2.4 Timer X RESET Initialization SEI CLD CLT 10000X002 CPUM(Address 3B16) Wait until f(XIN) oscillation is stabilized (Note 1) 00000X002 CPUM(Address 3B16) CNTR0 interrupt processing routine X: This bit is not used here. Set it to "0" or "1" arbitrary. Set "0" to the CNTR0 interrupt enable bit. (CNTR0 interrupt disabled) Set "0" to the timer X interrupt enable bit. (Timer X interrupt disabled) Timer X is read out. RTI Set port P14 to the input mode. Set timer X mode register 1 0 1 01 1 TXM(Address 2B16) Pulse width measurement mode Falling edge Timer X count stop Error processing at incorrect period input Timer X interrupt processing routine Set timer count source set register 10 00 TCSS(Address 2E16) Timer Y count source: f(XIN)/16 selected Error processing Set value to timer X (Note 2) "FF16" "FF16" Prescaler X (Address 2C16) Timer X (Address 2D16) RTI Set "0" to the CNTR0 interrupt request bit. Set "0" to the timer X interrupt request bit. Set "1" to the CNTR0 interrupt enable bit. (CNTR0 interrupt enabled) Set "1" to the timer X interrupt enable bit. (Timer X interrupt enabled) Set timer X mode register 1 0 0 11 Notes 1: For the concrete time, ask the oscillator manufacture. 2: About 250 ms = 1/4.19 MHz 16 (FF16+ 1) (FF16 + 1) Timer X division ratio Prescaler X setting value Timer X setting value TXM(Address 2B16) Timer X count start CLI Timer X interrupt processing Processing CNTR0 interrupt processing END Fig. 2.4.26 Example of control procedure Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-61 APPLICATION 7540 Group 2.4 Timer X 2.4.7 Notes on timer X Notes on using each mode of timer X are described below. (1) Count source f(XIN) can be used only when a ceramic oscillator or an on-chip oscillator is used. Do not use f(XIN) at RC oscillation. (2) Pulse output mode In order to use CNTR0 pin, set "1" to bit 4 of the port P1 direction register (output mode). In order to use TXOUT pin, set "1" to bit 3 of the port P0 direction register (output mode). CNTR0 interrupt active edge depends on the CNTR0 active edge switch bit. When this bit is "0", the CNTR0 interrupt request bit is set to "1" at the falling edge of CNTR0 pin input signal. When this bit is "1", the CNTR0 interrupt request bit is set to "1" at the rising edge of CNTR0 pin input signal. (3) Pulse width measurement mode In order to use CNTR0 pin, set "1" to bit 4 of the port P1 direction register (output mode). CNTR0 interrupt active edge depends on the CNTR0 active edge switch bit. When this bit is "0", the CNTR0 interrupt request bit is set to "1" at the falling edge of CNTR0 pin input signal. When this bit is "1", the CNTR0 interrupt request bit is set to "1" at the rising edge of CNTR0 pin input signal. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-62 APPLICATION 7540 Group 2.5 Timer Y and timer Z 2.5 Timer Y and timer Z This paragraph explains the registers setting method and the notes relevant to the timer Y and timer Z. 2.5.1 Memory map 000116 000716 001616 001716 002016 002116 002216 002316 002416 002516 002616 002716 002A16 002E16 Port P0 direction register (P0D) Port P3 direction register (P3D) Pull-up control register (PULL) Port P1P3 control register (P1P3C) Timer Y, Z mode register (TYZM) Prescaler Y (PREY) Timer Y secondary (TYS) Timer Y primary (TYP) Timer Y, Z waveform output control register (PUM) Prescaler Z (PREZ) Timer Z secondary (TZS) Timer Z primary (TZP) One-shot start register (ONS) Timer count source set register (TCSS) 003A16 003B16 003C16 003D16 003E16 003F16 Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Fig. 2.5.1 Memory map of registers relevant to timer Y and timer Z Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-63 APPLICATION 7540 Group 2.5 Timer Y and timer Z 2.5.2 Relevant registers Port P0 direction register b7 b6 b5 b4 b3 b2 b1 b0 Port P0 direction register (P0D) [Address : 01 16] B Name Function 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode At reset RW 0 Port P0 direction register 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 Fig. 2.5.2 Structure of Port P0 direction register Port P3 direction register b7 b6 b5 b4 b3 b2 b1 b0 Port P3 direction register (P3D) [Address : 07 16] B Name Function 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode At reset RW 0 Port P3 direction register 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 Note: The 32-pin package versions have nothing to be allocated for the following: *Bits 5 and 6 of P3D. Fig. 2.5.3 Structure of Port P3 direction register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-64 APPLICATION 7540 Group 2.5 Timer Y and timer Z Pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 Pull-up control register (PULL) [Address : 16 16] Name B P00 pull-up control bit 0 1 P01 pull-up control bit 2 P02, P03 pull-up control bit 3 P04 - P07 pull-up control bit 4 P30 - P33 pull-up control bit 5 P34 pull-up control bit 6 P35, P36 pull-up control bit 7 P37 pull-up control bit Function 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On At reset RW 0 0 0 0 0 0 0 0 Notes 1: Pins set to output are disconnected from the pull-up control. 2: Keep setting the P3 5, P36 pull-up control bit to "1" (initial value: 0) for the 32-pin package versions. Fig. 2.5.4 Structure of Pull-up control register Port P1P3 control register b7 b6 b5 b4 b3 b2 b1 b0 Port P1P3 control register (P1P3C) [Address : 17 16] B Name Function 0 : CMOS level 1 : TTL level 0 : CMOS level 1 : TTL level 0 : CMOS level 1 : TTL level At reset RW 0 P37/INT0 input level selection bit 1 P36/INT1 input level selection bit (Note) 2 P10, P12,P13 input level selection bit 0 0 0 0 0 0 0 0 3 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 4 5 6 7 Note: Keep setting the P3 6/INT1 input level selection bit to "0" (initial value) for the 32-pin package version. Fig. 2.5.5 Structure of Port P1P3 control register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-65 APPLICATION 7540 Group 2.5 Timer Y and timer Z Timer Y, Z mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer Y, Z mode register (TYZM) [Address : 20 16) B 0 Name Timer Y operating mode bit Function 0 : Timer mode 1 : Programmable waveform generation mode At reset RW 0 1 Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "0". 0 : Write to latch and timer 2 Timer Y write control bit simultaneously (Note) 1 : Write to only latch 0 : Count start 3 Timer Y count stop bit 1 : Count stop 0 0 0 0 4 Timer Z operating mode bits b5 b4 5 0 0 : Timer mode 0 1 : Programmable waveform generation mode 1 0 : Programmable one-shot generation mode 1 1 : Programmable wait one-shot generation mode 0 : Write to latch and timer simultaneously 1 : Write to only latch 0 : Count start 1 : Count stop 0 6 Timer Z write control bit (Note) 0 7 Timer Z count stop bit 0 Note: When modes other than the timer mode, set these bits to "1". Fig. 2.5.6 Structure of Timer Y, Z mode register Prescaler Y, Prescaler Z b7 b6 b5 b4 b3 b2 b1 b0 Prescaler Y (PREY) [Address : 2116] Prescaler Z (PREZ) [Address : 2516] B Function * While the corresponding timer is stopped, the value set in this register is written to both prescaler and the corresponding prescaler latch at the same time. * While the corresponding timer is operating, the value set in this register is written to as follows; When the timer write control bit is "0", the value is written to prescaler latch and prescaler at the same time. When the timer write control bit is "1", the value is written to prescaler latch only. * When this register is read out, the count value of the corresponding prescaler is read out. At reset RW 0 * Set a count value of each prescaler. 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 Fig. 2.5.7 Structure of Prescaler Y, Prescaler Z Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-66 APPLICATION 7540 Group 2.5 Timer Y and timer Z Timer Y secondary, Timer Z secondary b7 b6 b5 b4 b3 b2 b1 b0 Timer Y secondary, Timer Z secondary (TYS, TZS) [Address : 22 16, 2616] At reset B Function 0 *Set a count value of the corresponding timer. *The value set in this register is written to the corresponding 1 secondary latch at the same time. *These are read disabled bits. 2 When these bits are read out, the values are undefined. 1 1 1 1 1 1 1 1 RW 3 4 5 6 7 Fig. 2.5.8 Structure of Timer Y secondary, Timer Z secondary Timer Y primary, Timer Z primary b7 b6 b5 b4 b3 b2 b1 b0 Timer Y primary, Timer Z primary (TYP, TZP) [Address : 23 16, 2716] At reset B Function *When the corresponding timer is stopped, the value set in this register is written to both the corresponding primary latch and the corresponding timer at the same time. *When the corresponding timer is operating, the value set in this register is written as follows; timer write control bit = 0: the value is written to both the corresponding primary latch and the corresponding timer at the same time. timer write control bit = 1: the value is written to the corresponding primary latch. *When these bits are read out, the count value of the corresponding timer is read out (Note). RW 0 *Set a count value of the corresponding timer. 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 Note: The primary count value is read out at the primary interval, the secondary count value is read out at the secondary interval. Fig. 2.5.9 Structure of Timer Y primary, Timer Z primary Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-67 APPLICATION 7540 Group 2.5 Timer Y and timer Z Timer Y, Z waveform output control register b7 b6 b5 b4 b3 b2 b1 b0 Timer Y, Z waveform output control register (PUM) [Address : 24 16] At reset B 0 1 2 3 4 5 6 7 Name Timer Y primary waveform extension control bit Timer Y secondary waveform extension control bit Timer Z primary waveform extension control bit Timer Z secondary waveform extension control bit Function RW 0 : Waveform not extended 1 : Waveform extended 0 : Waveform not extended 1 : Waveform extended 0 : Waveform not extended 1 : Waveform extended 0 : Waveform not extended 1 : Waveform extended 0 : "L" output Timer Y output level latch 1 : "H" output 0 : "L" output Timer Z output level latch 1 : "H" output 0 : INT0 pin one-shot trigger invalid INT0 pin one-shot trigger 1 : INT0 pin one-shot trigger valid control bit (Note) INT0 pin one-shot trigger active 0 : Falling edge trigger 1 : Rising edge trigger edge selection bit ( Note) 0 0 0 0 0 0 0 0 Note: Stop timer Z to change the values of these bits. Fig. 2.5.10 Structure of Timer Y, Z waveform output control register One-shot start register b7 b6 b5 b4 b3 b2 b1 b0 One-shot start register (ONS) [Address : 2A 16] B Name Function 0 : One-shot stop 1 : One-shot start At reset RW 0 Timer Z one-shot start bit 0 0 0 0 0 0 0 0 1 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 2 3 4 5 6 7 Fig. 2.5.11 Structure of One-shot start register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-68 APPLICATION 7540 Group 2.5 Timer Y and timer Z Timer count source set register b7 b6 b5 b4 b3 b2 b1 b0 0 Timer count source set register (TCSS) [Address : 2E16] B Name b1 b0 Function 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : f(XIN) (Note 1) 1 1 : Not available b3 b2 At reset RW 0 Timer X count source selection bits 1 2 Timer Y count source selection bits 0 0 0 0 0 0 0 0 3 4 Timer Z count source selection bits 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : On-chip oscillator output (Note 2) 1 1 : Not available b5 b4 5 6 Fix this bit to "0". 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : Timer Y underflow 1 1 : Not available 7 Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "0". Notes 1: f(XIN) can be used as timer X count source only when using a ceramic oscillator or on-chip oscillator. Do not use it at RC oscillation. 2: System operates using an on-chip oscillator as a count source by setting the on-chip oscillator to oscillation enabled by bit 3 of CPUM. Fig. 2.5.12 Structure of Timer count source set register Interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt edge selection register (INTEDGE) [Address : 3A 16] B Name Function 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active At reset RW 0 INT0 interrupt edge selection bit 1 INT1 interrupt edge selection bit 0 0 0 0 0 0 0 2 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 3 4 5 6 7 P00 key-on wakeup enable bit 0 : Key-on wakeup enabled 1 : Key-on wakeup disabled 0 Fig. 2.5.13 Structure of Interrupt edge selection register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-69 APPLICATION 7540 Group 2.5 Timer Y and timer Z CPU mode register b7 b6 b5 b4 b3 b2 b1 b0 CPU mode register (CPUM) [Address : 3B16] B Name b1 b0 Function 0 0 1 1 0 : Single-chip mode 1 : Not available 0 : Not available 1 : Not available At reset RW 0 Processor mode bits (Note 1) 1 2 Stack page selection bit 0 0 0 0 0 0 0 3 On-chip oscillator oscillation control bit 4 XIN oscillation control bit 5 Oscillation mode selection bit (Note 1) 0 : 0 page 1 : 1 page 0 : On-chip oscillator oscillation enabled 1 : On-chip oscillator oscillation stop 0 : Ceramic or RC oscillation enabled 1 : Ceramic or RC oscillation stop 0 : Ceramic oscillation 1 : RC oscillation b7 b6 6 Clock division ratio selection bits 7 0 0 : = f(XIN)/2 (high-speed mode) 0 1 : = f(XIN)/8 (middle-speed mode) 1 0 : Applied from on-chip oscillator 1 1 : = f(XIN) (double-speed mode) (Note 2) 1 Notes 1: The bit can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. However, by reset the bit is initialized and can be rewritten, again. (It is not disable to write any data to the bit for emulator MCU "M37540RSS".) 2: These bits are used only when a ceramic oscillation is selected. Do not use these when an RC oscillation is selected. Fig. 2.5.14 Structure of CPU mode register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-70 APPLICATION 7540 Group 2.5 Timer Y and timer Z Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address : 3C 16] B Name Function 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset RW 0 Serial I/O1 receive interrupt request bit 1 Serial I/O1 transmit interrupt request bit 2 INT0 interrupt request bit 3 INT1 interrupt request bit 4 Key-on wake up interrupt request bit 5 CNTR0 interrupt request bit 0 0 0 0 0 0 0 0 6 CNTR1 interrupt request bit 7 Timer X interrupt request bit : These bits can be cleared to "0" by program, but cannot be set to "1". Fig. 2.5.15 Structure of Interrupt request register 1 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2) [Address : 3D 16] B Name Function 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset RW 0 Timer Y interrupt request bit 1 Timer Z interrupt request bit 2 Timer A interrupt request bit 3 Serial I/O2 interrupt request bit 4 AD converter interrupt request bit 0 0 0 0 0 0 0 0 5 Timer 1 interrupt request bit 6 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 7 : These bits can be cleared to "0" by program, but cannot be set to "1". Fig. 2.5.16 Structure of Interrupt request register 2 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-71 APPLICATION 7540 Group 2.5 Timer Y and timer Z Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address : 3E 16] B Name Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset RW 0 Serial I/O1 receive interrupt enable bit 1 Serial I/O1 transmit interrupt enable bit 0 0 0 0 0 0 0 0 2 INT0 interrupt enable bit 3 INT1 interrupt enable bit 4 Key-on wake up interrupt enable bit 5 CNTR0 interrupt enable bit 6 CNTR1 interrupt enable bit 7 Timer X interrupt enable bit Fig. 2.5.17 Structure of Interrupt control register 1 Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 2 (ICON2) [Address : 3F 16] B Name Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset RW 0 Timer Y interrupt enable bit 1 Timer Z interrupt enable bit 0 0 0 0 0 0 0 0 2 Timer A interrupt enable bit 3 Serial I/O2 interrupt enable bit 4 AD conversion interrupt enable bit 5 Timer 1 interrupt enable bit 6 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 7 Fig. 2.5.18 Structure of Interrupt control register 2 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-72 APPLICATION 7540 Group 2.5 Timer Y and timer Z 2.5.3 Timer mode (timer Y and timer Z) The basic operation of Timer Y and Timer Z are the same. In this section, Timer Y is explained. (1) Operation description Prescaler Y counts the count source selected by the timer Y count source selection bits. Each time the count clock is input, the contents of Prescaler Y is decremented by 1. When the contents of Prescaler Y reach "0016", an underflow occurs at the next count clock, and the prescaler Y latch is reloaded into Prescaler Y and count continues. The division ratio of Prescaler Y is 1/(n+1) provided that the value of Prescaler Y is n. The contents of Timer Y is decremented by 1 each time the underflow signal of Prescaler Y is input. When the contents of Timer Y reach "0016", an underflow occurs at the next count clock, and the timer Y primary latch is reloaded into Timer Y and count continues. (In the timer mode, the contents of timer Y primary latch is counted. Timer Y secondary latch is not used in this mode.) The division ratio of Timer Y is 1/(m+1) provided that the value of Timer Y is m. Accordingly, the division ratio of Prescaler Y and Timer Y is provided as follows that the value of Prescaler Y is n and the value of Timer Y is m. Division ratio = 1 (n+1) (m+1) In the timer mode, writing to "latch only" or "latches and Prescaler Y and timer Y primary" can be selected by the setting value of the timer Y write control bit. Timer Y can stop counting by setting "1" to the timer Y count stop bit. Also, when timer Y underflows, the timer Y interrupt request bit is set to "1". Timer Y reloads the value of latch when counting is stopped by the timer count stop bit. (When timer is read out while timer is stopped, the value of latch is read. The value of timer can be read out only while timer is operating.) (2) Timer mode setting method Figure 2.5.19 shows the setting method for timer mode of Timer Y. When Timer Z is used, registers are set by the same method. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-73 APPLICATION 7540 Group 2.5 Timer Y and timer Z Process 1: Disable timer Y interrupt. b7 b0 0 Interrupt control register 2 (ICON2) [Address 3F16] Timer Y interrupt disabled Process 2: Set timer Y, Z mode register. b7 b0 1 0 Timer Y, Z mode register (TYZM) [Address 2016] Timer mode Timer Y write control bit 0: Write to latch and timer simultaneously 1: Write to only latch Timer Y count stop Process 3: Set timer Y count source (Note 1) b7 b0 0 Timer count source set register (TCSS) [Address 2E16] Timer Y count source selection bits b3 b2 0 0 1 1 0 : f(XIN)/16 1 : f(XIN)/2 0 : On-chip oscillator output (Note 2) 1 : Not available Notes 1: For timer Z, f(XIN), f(XIN)/2, or timer Y underflow can be selected. 2: Set the on-chip oscillator oscillation to be enabled by bit 3 (on-chip oscillator oscillation control bit) of CPU mode register. Process 4: Set the count value to timer Y. * Set the count value to prescaler Y and timer Y primary Prescaler Y (PREY) (Address 2116) Count value Timer Y primary (TYP) (Address 2316) Count value Note: In the timer mode, the timer Y secondary is not used. Process 5: In order not to execute the no requested interrupt processing, set "0" (no requested) to the timer Y interrupt request bit. b7 b0 0 Interrupt request register 2 (IREQ2) [Address 3D16] No timer Y interrupt request issued Process 6: When timer Y interrupt is used, set "1" (interrupt enabled) to the timer Y interrupt enable bit. b7 b0 1 Interrupt control register 2 (ICON2) [Address 3F16] Timer Y interrupt enabled Process 7: Start counting of timer Y. b7 b0 0 0 Timer Y, Z mode register (TYZM) [Address 2016] Timer Y count start Fig. 2.5.19 Setting method for timer mode Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-74 APPLICATION 7540 Group 2.5 Timer Y and timer Z (3) Application example of timer mode Outline: Pulses generated corresponding to the water flow rate are counted for a fixed period (100 ms), and the water flow rate during this period is calculated. Specifications: Pulses generated corresponding to the water flow rate are input to the P14/CNTR1 pin and counted using timer X. The contents of timer X are read in the timer Y interrupt processing routine generated after 100 ms from the start of counting pulses, and the water flow rate during 100 ms is calculated. Operation clock: f(XIN) = 8 MHz, high-speed mode Figure 2.5.20 shows an example of peripheral circuit, Figure 2.5.21 shows the method of measuring water flow rate, and Figure 2.5.21 shows an example of control procedure. 7540 Group Water flow rate sensor Water flow P14/CNTR0 Blades rotate in proportion to water flow and generate pulses. The faster the water flow, the shorter the pulse period. Fig. 2.5.20 Example of peripheral circuit 100 ms Timer Y interrupt request bit CNTR0 pin input Timer X counting (Note) Timer X, timer Y start counting. Timer Y interrupt processing routine * Timer X, timer Y stop counting. * Timer X is read out. Note: Counting rising edges. * Flow rate during 100 ms = (FF16-read value of timer Y) flow rate per pulse Fig. 2.5.21 Method of measuring water flow rate Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-75 APPLICATION 7540 Group 2.5 Timer Y and timer Z Flow rate measuring routine Set "0" to the CNTR0 interrupt enable bit. (CNTR0 interrupt disabled) Set "0" to the timer X interrupt enable bit. (Timer X interrupt disabled) Set "0" to the timer Y interrupt enable bit. (Timer Y interrupt disabled) Set port P14 to the input mode. Set timer X mode register 1 0 11 10 1 0 Timer Y interrupt processing routine Set timer X mode register 1 1 1 0 TXM(Address 2B16) Timer X count stop Set timer Y, Z mode register 10 0 TYZM(Address 2016) TXM(Address 2B16) Event counter mode Count at falling edge Timer X count stop Timer Y count stop (Prescaler X setting value "FF16" timer X setting value "FF16") - (Prescaler X count value, timer X count value) The numbeer of event within 100 ms RTI Set timer Y, Z mode register 10 0 TYZM(Address 2016) Timer mode W ritin g to la t c h a n d tim e r s im u lta n e o u s ly Timer Y count stop Set timer count source set register 10 00 TCSS(Address 2E16) Timer Y count source: f(XIN)/16 selected Set value to timer X "FF16" "FF16" Prescaler X (Address 2C16) Timer X (Address 2D16) Set value to timer Y (Note) "C716" "F916" Prescaler Y (Address 2116) Timer Y primary (Address 2316) Note : 100 ms = 1/8 MHz 16 (C716 + 1) (F916 + 1) Timer Y division ratio Prescaler Y setting value Timer Y primary setting value Set "0" to the timer Y interrupt request bit. Set "1" to the timer Y interrupt enable bit. (Timer Y interrupt enabled) Set timer X mode register 1 0 0 1 1 0 TXM(Address 2B16) Timer X count start Set timer Y, Z mode register 00 0 TYZM(Address 2016) Timer Y count start END Fig. 2.5.22 Example of control procedure Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-76 APPLICATION 7540 Group 2.5 Timer Y and timer Z 2.5.4 Programmable waveform generation mode (timer Y and timer Z) The basic operation of Timer Y and Timer Z are the same. In this section, Timer Y is explained. (1) Operation description In the programmable waveform generation mode, timer counts the setting value of timer Y primary (TYP) and the setting value of timer Y secondary (TYS) alternately, the waveform whose polarity is inverted each time Timer Y underflows is output from P01/TYOUT pin. When using this mode, be sure to set "1" to the timer Y write control bit to select "write to latch only". Also, set the port P01 direction registers to output mode. The active edge of output waveform is set by the timer Y output level latch. When "0" is set to the timer Y output level latch, "H" interval by the setting value of TYP or "L" interval by the setting value of TYS is output alternately. When "1" is set to the timer Y output level latch, "L" interval by the setting value of TYP or "H" interval by the setting value of TYS is output alternately. Also, in this mode, the primary interval and the secondary interval of the output waveform can be extended respectively for 0.5 cycle of timer count source clock by setting the timer Y primary waveform extension control bit (b2) and the timer Y secondary waveform extension control bit (b3) of PUM to "1". As a result, the waveforms of more accurate resolution can be output. When b2 and b3 of PUM are used, the frequency and duty of the output waveform are as follows; Waveform frequency: FYOUT= 2 (TMYCL) (2 (TYP+1)+EXPYP)+(2 (TYS+1)+EXPYS)) 2 (TYP+1)+EXPYP Duty: DYOUT= (2 (TYP+1)+EXPYP)+(2 (TYS+1)+EXPYS)) TMYCL: Timer Y count source (frequency) TYP: Timer Y primary TYS: Timer Y secondary EXPYP (1 bit): Timer Y primary waveform extension control bit EXPYS (1 bit): Timer Y secondary waveform extension control bit In the programmable waveform generation mode, when values of the TYP, TYS, EXPYP and EXPYS are changed, the output waveform is changed at the beginning (timer Y primary waveform interval) of waveform period. When the count values are changed, set values to the TYS, EXPYP and EXPYS first. After then, set the value to TYP. The values are set all at once at the beginning of the next waveform period when the value is set to TYP. (When writing at timer stop is executed, writing to TYP at last is required.) Timer Y can stop counting by setting "1" to the timer Y count stop bit. Also, when timer Y underflows, the timer Y interrupt request bit is set to "1". Timer Y reloads the value of latch when counting is stopped by the timer Y count stop bit. (When timer is read out while timer is stopped, the value of latch is read. The value of timer can be read out only while timer is operating.) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-77 APPLICATION 7540 Group 2.5 Timer Y and timer Z Notes 1: In the programmable waveform generation mode, values of TYS, EXPYP, and EXPYS are valid by writing to TYP because the setting to them is executed all at once by writing to TYP. Even when changing TYP is not required, write the same value again. 2: In the programmable waveform generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TYP and the timing of timer underflow during the secondary interval simultaneously. An example of a measurement is shown below. ex.) The underflow by the primary and the underflow by secondary are stored by polling etc. using timer Y interrupt. Writing is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (Depending on a primary and a secondary setting values, and primary write timing, it may be impossible.) 3: The waveform extension function by the timer Y waveform extension control bits can be used only when "0016" is set to Prescaler Y. When the value other than "0016" is set to Prescaler Y, be sure to set "0" to EXPYP and EXPYS. The waveform extension function by the timer Z waveform extension control bits can be used only when "0016" is set to Prescaler Z. When the value other than "0016" is set to Prescaler Z, be sure to set "0" to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used. 4: When using this mode, be sure to set "1" to the timer Y write control bit to select "write to latch only". 5: When TYS is read out, the undefined value is read out. However, while timer Y counts the setting value of TYS, the count value during the secondary interval can be obtained by reading the timer Y primary. 6: In order to use TYOUT pin, set "1" to bit 1 of the port P0 direction register (output mode). Figure 2.5.23 shows the timing diagram of the programmable waveform generation mode. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-78 APPLICATION 7540 Group 2.5 Timer Y and timer Z q When "0316" is set to TYP and "0216" is set to TYS. Timer Y count clock "0" is written Timer Y count stop bit Count start Timer Y secondary reload Timer Y primary reload Timer Y secondary reload Contents of timer Y 0316 0216 0116 0016 0216 0116 0016 Underflow Underflow 0316 0216 0116 0016 0216 0116 Underflow Timer Y interrupt request bit "0" is written (Note 2) (Note 2) (Note 2) Timer Y output level latch Waveform output start Initialized to "L" Waveform output inverted Waveform output inverted Waveform output inverted TYOUT pin output (Note 1) Secondary waveform extension Notes 1: In this case, timer Y primary waveform is not extended, timer Y secondary waveform is extended. 2: In this time, "0" is written to the timer Y interrupt request bit or the timer Y interrupt request bit is cleared to "0" by accepting the timer Y interrupt request. Fig. 2.5.23 Timing diagram of programmable waveform generation mode Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-79 APPLICATION 7540 Group 2.5 Timer Y and timer Z (2) Programmable waveform generation mode setting method Figure 2.5.24 and Figure 2.5.25 show the setting method for programmable waveform generation mode of timer Y. When timer Z is used, registers are set by the same method. Process 1: Disable timer Y interrupt. b7 b0 0 Interrupt control register 2 (ICON2) [Address 3F16] Timer Y interrupt disabled Process 2: Set timer Y, Z mode register. b7 b0 11 1 Timer Y, Z mode register (TYZM) [Address 2016] Programmable waveform generation mode Write to only latch (Note) Timer Y count stop Note: When using this mode, be sure to set "1" to the timer Y write control bit to select "write to latch only". Process 3: Set timer Y, Z waveform output control register. b7 b0 Timer Y, Z waveform output control register (PUM) [Address 2416] Timer Y primary waveform extension control bit (No te) 0: Waveform not extended 1: Waveform extended Timer Y secondary waveform extension control bit (Note) 0: Waveform not extended 1: Waveform extended Timer Y output level latch 0: Initial state at stop: "L", "H" interval by TYP setting value, "L" interval by TYS setting value 1: Initial state at stop: "H", "L" interval by TYP setting value, "H" interval by TYS setting value Note: The waveform extension function by the timer Y waveform extension control bits can be used only when "0016" is set to prescaler Y. When the value other than "0016" is set to prescaler Y, be sure to set "0" to EXPYP and EXPYS. The waveform extension function by the timer Z waveform extension control bits can be used only when "0016" is set to prescaler Z. When the value other than "0016" is set to prescaler Z, be sure to set "0" to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used. Process 4: Set TYOUT pin to the output (Note). b7 b0 1 Port P0 direction register (P0D) [Address 0116] Set P01/TYOUT pin as the output mode Note: For timer Z, set TZOUT pin as the output by bit 2 of P0D. Fig. 2.5.24 Setting method for programmable waveform generation mode (1) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-80 APPLICATION 7540 Group 2.5 Timer Y and timer Z Process 5: Set timer Y count source (Note 1). b7 b0 0 Timer count source set register (TCSS) [Address 2E16] Timer Y count source selection bits b3 b2 0 0 1 1 0 : f(XIN)/16 1 : f(XIN)/2 0 : On-chip oscillator output (Note 2) 1 : Not available Notes 1: For Timer Z, f(XIN)/16, f(XIN)/2, or timer Y underflow can be selected. However, when the timer Z waveform expansion function is used, do not select the timer Y underflow for the timer Z count source. 2: Set the on-chip oscillator oscillation to be enabled by bit 3 (on-chip oscillator oscillation control bit) of CPU mode register. Process 6: Set the count value to timer Y (Note 1). * Set the count value to prescaler Y, timer Y secondary and timer Y primary Prescaler Y (PREY) (Address 2116) (Note 2) Count value Timer Y secondary (TYS) (Address 2216) Count value Timer Y primary (TYP) (Address 2316) (Notes 3, 4) Count value Notes 1: In the programmable waveform generation mode, values of TYS, EXPYP, and EXPYS are valid by writing to TYP. Even when changing TYP is not required, write the same value again. 2: When the timer Y waveform extension function is used, be sure to set "0016" to prescaler Y. 3: In the programmable waveform generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TYP and the timing of timer Y underflow during the secondary interval simultanesously. 4: Count values of the primary interval and secondary interval can be checked by reading the TYP (TYS is undefined at read). Process 7: In order not to execute the no requested interrupt processing, set "0" (no requested) to the timer Y interrupt request bit. b7 b0 0 Interrupt request register 2 (IREQ2) [Address 3D16] No timer Y interrupt request issued Process 8: When Timer Y interrupt is used, set "1" (interrupt enabled) to the timer Y interrupt enable bit. b7 b0 1 Interrupt control register 2 (ICON2) [Address 3F16] Timer Y interrupt enabled Process 9: Start counting of timer Y. b7 b0 01 1 Timer Y, Z mode register (TYZM) [Address 2016] Timer Y count start Fig. 2.5.25 Setting method for programmable waveform generation mode (2) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-81 APPLICATION 7540 Group 2.5 Timer Y and timer Z (3) Application example of programmable waveform generation mode Outline: The waveform extension function is used and the waveform output is executed. Specifications: The "H" width generated by TYP and the "L" width generated by TYS are output. Set each waveform extension function to be valid, and set the duty ratio to be 2:1. The frequency is 40 kHz. Operation clock: f(XIN) = 8 MHz, high-speed mode Figure 2.5.26 shows an example of waveform output and Figure 2.5.27 shows an example of control procedure. q 40 kHz pulse is output Duty ratio 2 16.7 s : 1 8.3 s TYOUT pin output Waveform extended Waveform extended Fig. 2.5.26 Example of waveform output Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-82 APPLICATION 7540 Group 2.5 Timer Y and timer Z RESET Initialization SEI CLD CLT CPUM(Address 3B16) 10000X002 Wait until f(XIN) oscillation is stabilized (Note 1) CPUM(Address 3B16) 00000X002 X: This bit is not used here. Set it to "0" or "1" arbitrary. Set "0" to the timer Y interrupt enable bit. (Timer Y interrupt disabled) Set timer Y, Z mode register 11 1 TYZM(Address 2016) Programmable waveform generation mode Writing to only latch (Note 2) Timer Y count stop Set timer Y, Z waveform output control register 0 1 1 PUM(Address 2416) Timer Y primary waveform generation extended (Note 3) Timer Y secondary waveform generation extended (Note 3) Initial state: "L", TYP: "H" interval, TYS: "L" interval Set port P01 to the output mode. Set timer count source set register 10 01 TCSS(Address 2E16) Timer Y count source: f(XIN)/2 selected Set value to timer Y (Notes 3, 4, 5, 6) "0016" "2016" "4116" Prescaler Y (Address 2116) Timer Y secondary (Address 2216) Timer Y primary (Address 2316) Set "0" to the timer Y interrupt request bit. Set "1" to the timer Y interrupt enable bit. (Timer Y interrupt enabled) Set timer Y, Z mode register 01 1 Notes 1: For the concrete time, ask the oscillator manufacture. 2: When using this mode, be sure to select "write to latch only". 3: The waveform extension function by the timer Y waveform extension control bits can be used only when "0016" is set to prescaler Y. When the value other than "0016" is set to prescaler Y, be sure to set "0" to EXPYP and EXPYS. 4: In the programmable waveform generation mode, values of TYS, EXPYP, and EXPYS are valid by writing to TYP. Even when changing TYP is not required, write the same value again. 5: In the programmable waveform generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TYP and the timing of timer Y underflow during the secondary interval simultanesously. 6: Count values of the primary interval and secondary interval can be checked by reading TYP (TYS is undefined at read). TYZM(Address 2016) Timer Y count start CLI Processing Fig. 2.5.27 Example of control procedure Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-83 APPLICATION 7540 Group 2.5 Timer Y and timer Z 2.5.5 Programmable one-shot generation mode (timer Z) (1) Operation description In the programmable one-shot generation mode, the one-shot pulse by the setting value of timer Z primary can be output from P02/TZOUT pin by software or external trigger to the P37/INT0 pin. When using this mode, be sure to set "1" to the timer Z write control bit to select "write to latch only". Also, set the port P02 direction registers to output mode. In this mode, the timer Z secondary (TZS) is not used. The active edge of output waveform is set by the timer Z output level latch. When "0" is set to the timer Z output level latch, "H" pulse during the interval of the timer Z primary (TZP) setting value is output. When "1" is set to the timer Z output level latch, "L" pulse during the interval of the TZP setting value is output. Also, in this mode, the interval of the one-shot pulse output can be extended for 0.5 cycle of timer count source clock by setting the timer Z primary waveform extension control bit (EXPZP) to "1". As a result, the waveforms of more accurate resolution can be output. During the one-shot pulse output interval, the one-shot pulse output can be stopped forcibly by writing "0" to the timer Z one-shot start bit. In the programmable one-shot generation mode, when the count values are changed, set value to the EXPZP first. After then, set the value to TZP. The values are set all at once at the beginning of the next one-shot pulse when the value is set to TZP. (Even when writing at timer stop is executed, writing to TZP at last is required.) Timer Z can stop counting by setting "1" to the timer Z count stop bit. Also, when timer Z underflows, the timer Z interrupt request bit is set to "1". Timer Z reloads the value of latch when counting is stopped by the timer Z count stop bit. (When timer is read out while timer is stopped, the value of latch is read. The value of timer can be read out only while timer is operating.) Notes 1: In the programmable one-shot generation mode, the value of EXPZP becomes valid by writing to TZP. Even when changing TZP is not required, write the same value again. 2: In the programmable one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow simultaneously. An example of a measurement is shown below. ex.) The underflow of timer is stored by polling etc. using timer Z interrupt. Writing to primary is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (Depending on a primary setting value, primary write timing, software and timing of external trigger to INT0 pin, it may be impossible.) 3: The waveform extension function by the timer Z waveform extension control bits can be used only when "0016" is set to Prescaler Z. When the value other than "0016" is set to Prescaler Z, be sure to set "0" to EXPZP. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used. 4: When using this mode, be sure to set "1" to the timer Z write control bit to select "write to latch only". 5: In order to use TZOUT pin, set "1" to bit 2 of the port P0 direction register (output mode). 6: Stop Timer Z to change the INT0 pin one-shot trigger control bit and INT0 pin one-shot trigger active edge selection bit. Figure 2.5.28 shows the timing diagram of the programmable one-shot generation mode. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-84 APPLICATION 7540 Group 2.5 Timer Y and timer Z q When "0316" is set to TZP Timer Z count clock "0" is written Timer Z count stop bit "1" is written One-shot start bit Set to "1" by INT0 pin input trigger INT0 pin input (Note 1) Count start Timer Z primary reload Count start Timer Z primary reload Contents of timer Z 0316 0216 0116 0016 Underflow 0316 0216 0116 0016 0316 Underflow Timer Z interrupt request bit "0" is written (Note 3) Timer Z output level latch Waveform output start Waveform output end Waveform output start Waveform output end TZOUT pin output (Note 2) Initialized to "L" Waveform extension Waveform extension Notes 1: In this case, INT0 pin one-shot trigger valid. 2: In this case, timer Z primary waveform is extended. 3: In this time, "0" is written to the timer Z interrupt request bit or the timer Z interrupt request bit is cleared to "0" by accepting the timer Z interrupt request. Fig. 2.5.28 Timing diagram of programmable one-shot generation mode Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-85 APPLICATION 7540 Group 2.5 Timer Y and timer Z (2) Event counter mode setting method Figure 2.5.29 to Figure 2.5.31 show the setting method for programmable one-shot generation mode of timer Z. Process 1: Disable the interrupt. b7 b0 0 Interrupt control register 1 (ICON1) [Address 3E16] INT0 interrupt disabled b7 b0 0 Interrupt control register 2 (ICON2) [Address 3F16] Timer Z interrupt disabled Process 2: Set timer Y, Z mode register. b7 b0 1110 Timer Y, Z mode register (TYZM) [Address 2016] Programmable one-shot generation mode Write to only latch (Note) Timer Y count stop Note: When using this mode, be sure to select "write to latch only". Process 3: Set timer Y, Z waveform output control register. b7 b0 Timer Y, Z waveform output control register (PUM) [Address 2416] Timer Z primary waveform extension control bit (Note 1) 0: Waveform not extended 1: Waveform extended Timer Z output level latch 0: Initial state at stop: "L", "H" interval by TZP setting value, "L" interval by TZ S setting value 1: Initial state at stop: "H", "L" interval by TZP setting value, "H" interval by TZS setting value INT0 pin one-shot trigger control bit (Note 2) 0: INT0 pin one-shot trigger invalid 1: INT0 pin one-shot trigger valid INT0 pin one-shot trigger active edge selection bit (Note 2) 0: Falling edge trigger 1: Rising edge trigger Notes 1: The waveform extension function by the timer Z waveform extension control bits can be used only when "0016" is set to prescaler Z. When the value other than "0016" is set to prescaler Z, be sure to set "0" to EXPZP. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used. 2: Stop timer Z to change these bits. Process 4: Set TZOUT pin to the output (Note). b7 b0 1 Port P0 direction register (P0D) [Address 0116] Set P02/TZOUT pin as the output mode Fig. 2.5.29 Setting method for programmable one-shot generation mode (1) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-86 APPLICATION 7540 Group 2.5 Timer Y and timer Z Process 5: When the trigger by INT0 pin input is selected: Set port P3 direction register, pull-up control register and port P1P3 control register b7 b0 0 Port P3 direction register (P3D) [Address 0716] Set P37/INT0 pin as the input mode b7 b0 Pull-up control register (PULL) [Address 1616] P37 pull-up control bit 0: Pull-up Off 1: Pull-up On b7 b0 Port P1P3 control register (P1P3C) [Address 1716] P37/INT0 input level selection bit 0: CMOS level 1: TTL level Process 6: Set the timer Z count source. b7 b0 0 Timer count source set register (TCSS) [Address 2E16] Timer Z count source selection bits b5 b4 00 01 10 11 : f(XIN)/16 : f(XIN)/2 : Timer Y underflow (Note) : Not available Note: When the timer Z waveform extension function is used, do not select the timer Y underflow as the timer Z count source. Process 7: Set the one-shot pulse width (Note 1). * Set the count value to prescaler Z and timer Z primary Prescaler Z (PREZ) [Address 2516] (Note 2) Count value Timer Z primary (TZP) [Address 2716] (Note 3) Count value Notes 1: In the programmable one-shot generation mode, TZS is not used. When the count setting value is changed, value of EXPZP is valid by writing to TZP. Even when changing TZP is not required, write the same value again. 2: When the timer Z waveform extension function is used, be sure to set "0016" to prescaler Z. 3: In the programmable one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer Z underflow simultanesously. Process 8: Set the standby state to accept the one-shot start trigger (Note). b7 b0 0110 Timer Y, Z mode register (TYZM) [Address 2016] Timer Z count start Note: When the INT0 pin one-shot trigger control bit of PUM is set to"valid", timer Z counting is started by the input of trigger to INT0 pin after this setting. Fig. 2.5.30 Setting method for programmable one-shot generation mode (2) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-87 APPLICATION 7540 Group 2.5 Timer Y and timer Z Process 9: In order not to execute the no requested interrupt processing, set "0" (no requested) to the timer Z interrupt request bit. b7 b0 0 Interrupt request register 2 (IREQ2) [Address 3D16] No Timer Z interrupt request issued q When the INT0 pin one-shot trigger control bit of PUM is set to "valid" and the INT0 interrupt is used, set the following; b7 b0 Interrupt edge selection register (INTEDGE) [Address 3A16] INT0 interrupt edge selection bit 0: Falling edge active 1: Rising edge active b7 b0 0 Interrupt request register 1 (IREQ1) [Address 3C16] No INT0 interrupt request issued Process 10: When the interrupt is used, set "1" (interrupt enabled) to the corresponding interrupt enable bit. b7 b0 1 Interrupt control register 1 (ICON1) [Address 3E16] INT0 interrupt enabled (No te) b7 b0 1 Interrupt control register 2 (ICON2) [Address 3F16] Timer Y interrupt enabled Note: When the INT0 pin one-shot trigger control bit is set to "valid", the INT0 interrupt can be accepted after this setting. Process 11: Start counting of timer Z. b7 b0 1 One-shot start register (ONS) [Address 2A16] Timer Z one-shot start (Note) q When the INT0 pin one-shot trigger control bit of PUM is set to "valid", the timer Z count is started by input of trigger to the INT0 pin. Note: Pulse is output from TZOUT pin. After output, this bit is initialized to "0". Fig. 2.5.31 Setting method for programmable one-shot generation mode (3) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-88 APPLICATION 7540 Group 2.5 Timer Y and timer Z (3) Application example of programmable one-shot generation mode Outline: The phase control signal to the load is output by using the programmable one-shot generation mode of Timer Z. Specifications: The phase control signal to the load is output from the P02/TZOUT pin using the programmable one-shot generation mode of timer Z. * Count source: f(XIN)/16 * Rising edges of the signal input to the P37/INT0 pin from the trigger detection circuit are detected. * A triac is turned on at the "H" level. The period of the feedback signal input from the load is measured, analyzed, and used to adjust the phase control signal. Operation clock: f(XIN) = 8 MHz, high-speed mode For the measurement of the period of the feedback signal, refer to the period measurement mode of the using timer. Figure 2.5.32 shows an example of peripheral circuit, Figure 2.5.33 shows an example of an operation timing, and Figure 2.5.34 shows an example of a control procedure. 7540 Group Feedback signal Load Phase control signal Trigger detection circuit Port P02/TZOUT P37/INT0 VAC Fig. 2.5.32 Example of peripheral circuit VAC power source INT0 pin input Contents of timer Z RL Writing to latch in INT0 interrupt processing routine RL RL RL RL RL 000016 UF UF UF UF UF UF TZOUT pin output Fig. 2.5.33 Example of operation timing Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-89 APPLICATION 7540 Group 2.5 Timer Y and timer Z RESET Initialization SEI CLD CLT 10000X002 CPUM(Address 3B16) Wait until f(XIN) oscillation is stabilized (Note 1) CPUM(Address 3B16) 00000X002 INT0 interrupt processing routine Set "0" to the timer Z interrupt enable bit. (Timer Z interrupt disabled) Set timer Y, Z mode register 1110 TYZM(Address 2016) Programmable one-shot generation mode Writing to only latch (Note 2) Timer Z count stop Set timer Y, Z waveform output control register 110 1 PUM(Address 2416) Timer Z primary waveform generation extended (Note 3) Initial state: "L", TZP: "H" interval, TZS: "L" interval, stop at "L" after underflow INT0 pin one-shot trigger valid (Note 4) INT0 pin rising edge trigger (Note 4) X: This bit is not used here. Set it to "0" or "1" arbitrary. Change of timer Z RTI Set port P02 to the output mode. Set port P37 to the input mode. Set pull-up control register Set port P1P3 control register Set timer count source set register (Note 3) 1000 TCSS(Address 2E16) Timer Z count source: f(XIN)/16 selected Set value to timer Z (Notes 3, 5, 6) Prescaler Z (Address 2516) Timer Z primary (Address 2716) Set the standby state to accept one-shot start trigger 0110 TYZM(Address 2016) Timer Z count start (Note 7) Set the interrupt edge selection register 1 INTEDGE(Address 3A16) INT0 rising edge active Notes 1: For the concrete time, ask the oscillator manufacture. 2: When using this mode, be sure to select "write to latch only". 3: The waveform extension function by the timer Z waveform extension control bits can be used only when "0016" is set to prescaler Z. When the value other than "0016" is set to prescaler Z, be sure to set "0" to EXPZP. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used. 4: Stop timer Z to change the INT0 pin one-shot trigger control bit and INT0 one-shot trigger active edge selection bit. 5: In the programmable one-shot generation mode, the value of EXPZP is valid by writing to TZP. Even when changing TZP is not required, write the same value again. 6: In the programmable one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer Z underflow simultanesously. 7: In this state, timer count is not started. Set "0" to the INT0 interrupt request bit. Set "1" to the INT0 interrupt enable bit. (INT0 interrupt enabled) CLI Phase control processing q Period measurement of feedback signal q Analyze of measured value (determination of timer Z setting value) Fig. 2.5.34 Example of control procedure Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-90 APPLICATION 7540 Group 2.5 Timer Y and timer Z 2.5.6 Programmable wait one-shot generation mode (timer Z) (1) Operation description In the programmable wait one-shot generation mode, the one-shot pulse by the setting value of timer Z secondary (TZS) can be output from P02/TZOUT pin by software or external trigger to P37/INT0 pin after the wait by the setting value of the timer Z primary (TZP). When using this mode, be sure to set "1" to the timer Z write control bit to select "write to latch only". Also, set the port P02 direction registers to output mode. The active edge of output waveform is set by the timer Z output level latch. When "0" is set to the timer Z output level latch, after the wait during the interval of the TZP setting value, "H" pulse during the interval of the TZS setting value is output. When "1" is set to the timer Z output level latch, after the wait during the interval of the TZP setting value, "L" pulse during the interval of the TZS setting value is output. Also, in this mode, the intervals of the wait and the one-shot pulse output can be extended for 0.5 cycle of timer count source clock by setting the timer Z primary waveform extension control bit (EXPZP) and the timer Z secondary waveform extension control bit (EXPZS) to "1". As a result, the waveforms of more accurate resolution can be output. In the programmable wait one-shot generation mode, the trigger by software or the external INT0 pin can be accepted by writing "0" to the timer Z count stop bit after the count value is set. (At the time when "0" is written to the timer Z count stop bit, Timer Z stops.) By writing "1" to the timer Z one-shot start bit, or by inputting the valid trigger to the INT0 pin after the trigger to the INT0 pin becomes valid by writing "1" to the INT0 pin one-shot trigger control bit, Timer Z starts counting. While Timer Z counts the TZP, the initial value of the TZOUT pin output is retained. When Timer Z underflows, the value of TZS is reloaded, at the same time, the output of TZOUT pin is inverted. When Timer Z underflows, the output of TZOUT pin is inverted again and Timer Z stops. When also the trigger of INT0 pin is accepted, the contents of the one-shot start bit is changed to "1" by hardware. The falling or rising can be selected as the edge of the valid trigger of INT0 pin by the INT0 pin oneshot trigger edge selection bit. During the wait interval and the one-shot pulse output interval, the one-shot pulse output can be stopped forcibly by writing "0" to the timer Z one-shot start bit. In the programmable wait one-shot generation mode, when the count values are changed, set values to the TZS, EXPZP and EXPZS first. After then, set the value to TZP. The values are set all at once at the beginning of the next wait interval when the value is set to TZP. (When writing at timer stop is executed, writing to TZP at last is required.) Timer Z can stop counting by setting "1" to the timer Z count stop bit. Also, when timer Z underflows, the timer Z interrupt request bit is set to "1". Timer Z reloads the value of latch when counting is stopped by the timer Z count stop bit. (When timer is read out while timer is stopped, the value of latch is read. The value of timer can be read out only while timer is operating.) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-91 APPLICATION 7540 Group 2.5 Timer Y and timer Z Notes 1: In the programmable wait one-shot generation mode, values of TZS, EXPZP and EXPZS are valid by writing to TZP. Even when changing TZP is not required, write the same value again. 2: In the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow during the secondary interval simultaneously. An example of a measurement is shown below. ex.) The underflow by the primary and the underflow by secondary are stored by polling etc. using timer Z interrupt. Writing to primary is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (Depending on a primary setting value, primary write timing, software and timing of external trigger to INT0 pin, it may be impossible.) 3: The waveform extension function by the timer Z waveform extension control bits can be used only when "0016" is set to Prescaler Z. When the value other than "0016" is set to Prescaler Z, be sure to set "0" to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used. 4: When using this mode, be sure to set "1" to the timer Z write control bit to select "write to latch only". 5: When TZS is read out, the undefined value is read out. However, while Timer Z counts the setting value of TZS (during one-shot output), the count value during the secondary interval can be obtained by reading TZP. 6: In order to use TZOUT pin, set "1" to bit 2 of the port P0 direction register (output mode). 7: Stop Timer Z to change the INT0 pin one-shot trigger control bit and INT0 pin one-shot trigger active edge selection bit. Figure 2.5.35 shows the timing diagram of the programmable wait one-shot generation mode. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-92 APPLICATION 7540 Group 2.5 Timer Y and timer Z q When "0316" is set to TZP and "0416" is set to TZS. Timer Z count clock "0" is written Timer Z count stop bit "1" is written One-shot start bit Set to "1" by INT0 pin input trigger INT0 pin input (Note 1) Count start Timer Z secondary reload Count start Timer Z primary reload Contents of timer Z 0316 0216 0116 0016 Underflow 0416 0316 0216 0116 0016 Underflow 0316 Timer Z interrupt request bit "0" is written (Note 3) (Note 3) Timer Z output level latch Wait start Initialized to "L" Waveform output start Waveform output end TZOUT pin output (Note 2) Waveform extension Notes 1: In this case, INT0 pin one-shot trigger valid (rising edge trigger selected). 2: In this case, timer Z primary waveform is extended, timer Z secondary waveform is not extended. 3: In this time, "0" is written to the timer Z interrupt request bit or the timer Z interrupt request bit is cleared to "0" by accepting the timer Z interrupt request. Fig. 2.5.35 Timing diagram of programmable wait one-shot generation mode Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-93 APPLICATION 7540 Group 2.5 Timer Y and timer Z (2) Programmable wait one-shot generation mode setting method Figure 2.5.36 to Figure 2.5.38 show the setting method for programmable wait one-shot generation mode of Timer Z. Process 1: Disable interrupt. b7 b0 0 Interrupt control register 1 (ICON1) [Address 3E16] INT0 interrupt disabled b7 b0 0 Interrupt control register 2 (ICON2) [Address 3F16] Timer Z interrupt disabled Process 2: Set timer Y, Z mode register. b7 b0 1111 Timer Y, Z mode register (TYZM) [Address 2016] Programmable wait one-shot generation mode Write to only latch (Note) Timer Y count stop Note: When using this mode, be sure to select "write to latch only". Process 3: Set timer Y, Z waveform output control register. b7 b0 Timer Y, Z waveform output control register (PUM) [Address 2416] Timer Z primary waveform extension control bit (Note 1) 0: Waveform not extended 1: Waveform extended Timer Z secondary waveform extension control bit (Note 1) 0: Waveform not extended 1: Waveform extended Timer Z output level latch 0: "L" level is output at timer stop. When count is started, "L" level is output during the TZP interval (wait), and them, "H" level is output during the TZS interval (one-shot) and timer Z output is stopped at "L" level by underflow. 1: "H" level is output at timer stop. When count is started, "H" level is output during the TZP interval (wait), and them, "L" level is output during the TZS interval (one-shot) and timer Z output is stopped at "H" level by underflow. INT0 pin one-shot trigger control bit (Note 2) 0: INT0 pin one-shot trigger invalid 1: INT0 pin one-shot trigger valid INT0 pin one-shot trigger active edge selection bit (Note 2) 0: Falling edge trigger 1: Rising edge trigger Notes 1: The waveform extension function by the timer Z waveform extension control bits can be used only when "0016" is set to prescaler Z. When the value other than "0016" is set to prescaler Z, be sure to set "0" to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used. 2: Stop Timer Z to change these bits. Process 4: Set TZOUT pin to the output. b7 b0 1 Port P0 direction register (P0D) [Address 0116] Set P02/TZOUT pin as the output mode Fig. 2.5.36 Setting method for programmable wait one-shot generation mode (1) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-94 APPLICATION 7540 Group 2.5 Timer Y and timer Z Process 5: When the trigger by INT0 pin input is selected: Set port P3 direction register, pull-up control register and port P1P3 control register b7 b0 0 Port P3 direction register (P3D) [Address 0716] Set P37/INT0 pin to the input mode b7 b0 Pull-up control register (PULL) [Address 1616] P37/INT0 pull-up control bit 0: Pull-up Off 1: Pull-up On b7 b0 Port P1P3 control register (P1P3C) [Address 1716] P37/INT0 input level selection bit 0: CMOS level 1: TTL level Process 6: Set the timer Z count source. b7 b0 0 Timer count source set register (TCSS) [Address 2E16] Timer Z count source selection bits b5 b4 00 01 10 11 : f(XIN)/16 : f(XIN)/2 : Timer Y underflow (Note) : Not available Note: When the timer Z waveform extension function is used, do not select the timer Y underflow for the timer Z count source. Process 7: Set the wait interval, one-shot pulse width (Note 1). * Set the wait interval to the timer Z primary, and one-shot pulse width to the timer Z secondary. Prescaler Z (PREZ) [Address 2516] (Note 2) Count value Timer Z secondary (TZS) [Address 2616] Count value Timer Z primary (TZP) [Address 2716] Count value Notes 1: In the programmable wait one-shot generation mode, values of TZS, EXPZP, and EXPZS are valid by writing to TZP. Even when changing TZP is not required, write the same value again. 2: When the timer Z waveform extension function is used, be sure to set "0016" to prescaler Z. 3: In the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer Z underflow during the secondary interval simultanesously. 4: Count values of the primary interval (during wait) and secondary interval (during one-shot output) can be checked by reading TZP (TZS is undefined at read). Fig. 2.5.37 Setting method for programmable wait one-shot generation mode (2) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-95 APPLICATION 7540 Group 2.5 Timer Y and timer Z Process 8: Set the standby state to accept the one-shot start trigger (Note). b7 b0 011 1 Timer Y, Z mode register (TYZM) [Address 2016] Timer Z count start Note: When the INT0 pin one-shot trigger control bit of PUM is set to "valid", timer Z counting is started by the input of trigger to INT0 pin after this setting. Process 9: In order not to execute the no requested interrupt processing, set "0" (no requested) to the timer Z interrupt request bit. b7 b0 0 Interrupt request register 2 (IREQ2) [Address 3D16] No timer Z interrupt request issued q When the INT0 pin one-shot trigger control bit is set to "valid" and the INT0 interrupt is used, set the following; b7 b0 Interrupt edge selection register (INTEDGE) [Address 3A16] INT0 interrupt edge selection bit 0: Falling edge active 1: Rising edge active b7 b0 0 Interrupt request register 1 (IREQ1) [Address 3C16] No INT0 interrupt request issued Process 10: When the interrupt is used, set "1" (interrupt enabled) to the corresponding interrupt enable bit. b7 b0 1 Interrupt control register 1 (ICON1) [Address 3E16] INT0 interrupt enabled (Note) b7 b0 1 Interrupt control register 2 (ICON2) [Address 3F16] Timer Z interrupt enabled Note: When the INT0 pin one-shot trigger control bit is set to "valid", the INT0 interrupt can be accepted after this setting. Process 11: Start counting of timer Z. b7 b0 1 One-shot start register (ONS) [Address 2A16] Timer Z one-shot start (Note) q When the INT0 pin one-shot trigger control bit of PUM is set to "valid", the timer Z count is started by input of trigger to the INT0 pin. Note: Pulse is output from TZOUT pin. After output, this bit is initialized to "0". Fig. 2.5.38 Setting method for programmable wait one-shot generation mode (3) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-96 APPLICATION 7540 Group 2.5 Timer Y and timer Z (3) Application example of programmable wait one-shot generation mode Outline: The wait one-shot pulse synchronized with the PWM waveform output from the P01/TYOUT pin is generated from Timer Z by using the programmable waveform generation mode of Timer Y. Specifications: TYOUT pin is connected to the P37/INT0 pin. The wait one-shot pulse is output by the INT0 pin input as trigger. Operation clock: f(XIN) = 8 MHz, high-speed mode As for the usage of Timer Y, refer to the above mentioned programmable waveform generation mode. Figure 2.5.39 shows an example of waveform generation and peripheral circuit. Figure 2.5.40 shows an example of control procedure. 7540 Group P01/TYOUT P37/INT0 P02/TZOUT Timer Z active Timer Z active Timer Z active Fig. 2.5.39 Example of waveform generation and peripheral circuit Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-97 APPLICATION 7540 Group 2.5 Timer Y and timer Z Wait one-shot generation routine Set "0" to the timer Z interrupt enable bit. (Timer Z interrupt disabled) Set timer Y, Z mode register 1111 Timer Z interrupt processing routine TYZM(Address 2016) Programmable wait one-shot generation mode Writing to only latch (Note 2) Timer Z count stop Change of timer Z Set timer Y, Z waveform output control register 111 00 PUM(Address 2416) Timer Z primary waveform generation not extended (Note 2) Timer Z secondary waveform generation not extended (Note 2) Initial state: T ZP: "H" interval, TZS: "L" interval after underflow Stop at "H" after underflow INT0 pin one-shot trigger valid (Note 3) INT0 pin rising edge trigger (Note 3) RTI Set port P02 to the output mode. Set port P37 to the input mode. Set pull-up control register Set port P1P3 control register Set timer count source set register (Note 3) 10 TCSS(Address 2E16) Timer Z count source selected Set value to timer Z (Notes 2, 4, 5, 6) Prescaler Z (Address 2516) Timer Z secondary (A ddress 261 6) Timer Z primary (Address 2716) Set the standby state to accept one-shot start trigger 0111 TYZM(Address 2016) Timer Z count start (Note 7) Set interrupt edge selection register 1 Notes 1: When using this mode, be sure to select "write to latch only". 2: The waveform extension function by the timer Z waveform extension control bits can be used only when "0016" is set to prescaler Z. When the value other than "0016" is set to prescaler Z, be sure to set "0" to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used. 3: Stop timer Z to change the INT0 pin one-shot trigger control bit and INT0 one-shot trigger active edge selection bit. 4: In the programmable wait one-shot generation mode, values of TZS, EXPZP, and EXPZS are valid by writing to TZP. Even when changing TZP is not required, write the same value again. 5: In the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer Z underflow simultanesously. 6: Count values of the primary interval (during wait) and secondary interval (during one-shot output) can be checked by reading TZP (TZS is undefined at read). 7: In this state, timer count is not started. INTEDGE(Address 3A16) INT0 rising edge active Set "0" to the imer Z interrupt request bit. Set "1" to the timer Z interrupt enable bit. (Timer Z interrupt enabled) RTS Fig. 2.5.40 Example of control procedure Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-98 APPLICATION 7540 Group 2.5 Timer Y and timer Z 2.5.7 Notes on timer Y and timer Z Notes on using each mode of Timer Y and Timer Z are described below. (1) Timer mode (timer Y and timer Z) In the timer mode, TYP and TYS is not used. (2) Programmable waveform generation mode (timer Y and timer Z) In the programmable waveform generation mode, values of TYS, EXPYP, and EXPYS are valid by writing to TYP because the setting to them is executed all at once by writing to TYP. Even when changing TYP is not required, write the same value again. In the programmable waveform generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TYP and the timing of timer underflow during the secondary interval simultaneously. An example of a measurement is shown below. ex.) The underflow by the primary and the underflow by secondary are stored by polling etc. using timer Y interrupt. Writing to primary is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (Depending on a primary and a secondary setting values, and primary write timing, it may be impossible.) The waveform extension function by the timer Y waveform extension control bits can be used only when "0016" is set to Prescaler Y. When the value other than "0016" is set to Prescaler Y, be sure to set "0" to EXPYP and EXPYS. The waveform extension function by the timer Z waveform extension control bits can be used only when "0016" is set to Prescaler Z. When the value other than "0016" is set to Prescaler Z, be sure to set "0" to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used. When using this mode, be sure to set "1" to the timer Y write control bit to select "write to latch only". When TYS is read out, the undefined value is read out. However, while timer Y counts the setting value of TYS, the count value during the secondary interval can be obtained by reading the timer Y primary. In order to use TYOUT pin, set "1" to bit 1 of the port P0 direction register (output mode). (3) Programmable one-shot generation mode (timer Z) In the programmable one-shot generation mode, the value of EXPZP becomes valid by writing to TZP. Even when changing TZP is not required, write the same value again. In the programmable one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow simultaneously. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-99 APPLICATION 7540 Group 2.5 Timer Y and timer Z The waveform extension function by the timer Z waveform extension control bits can be used only when "0016" is set to Prescaler Z. When the value other than "0016" is set to Prescaler Z, be sure to set "0" to EXPZP. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used. An example of a measurement is shown below. ex.) The underflow of timer is stored by polling etc. using timer Z interrupt. Writing to primary is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (Depending on a primary setting value, primary write timing, software and timing of external trigger to INT0 pin, it may be impossible.) When using this mode, be sure to set "1" to the timer Z write control bit to select "write to latch only". In order to use TZOUT pin, set "1" to bit 2 of the port P0 direction register (output mode). Stop Timer Z to change the INT0 pin one-shot trigger control bit and INT0 pin one-shot trigger active edge selection bit. (4) Programmable wait one-shot generation mode (timer Z) In the programmable wait one-shot generation mode, values of TZS, EXPZP and EXPZS are valid by writing to TZP. Even when changing TZP is not required, write the same value again. An example of a measurement is shown below. ex.) The underflow by the primary and the underflow by secondary are stored by polling etc. using timer Z interrupt. Writing to primary is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (Depending on a primary setting value, primary write timing, software and timing of external trigger to INT0 pin, it may be impossible.) In the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow during the secondary interval simultaneously. The waveform extension function by the timer Z waveform extension control bit can be used only when "0016" is set to Prescaler Z. When the value other than "0016" is set to Prescaler Z, be sure to set "0" to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used. When using this mode, be sure to set "1" to the timer Z write control bits to select "write to latch only". When TZS is read out, the undefined value is read out. However, while Timer Z counts the setting value of TZS (during one-shot output), the count value during the secondary interval can be obtained by reading TZP. In order to use TZOUT pin, set "1" to bit 2 of the port P0 direction register (output mode). Stop Timer Z to change the INT0 pin one-shot trigger control bit and INT0 pin one-shot trigger active edge selection bit. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-100 APPLICATION 7540 Group 2.6 Serial I/O1 2.6 Serial I/O1 This paragraph explains the registers setting method and the notes relevant to the serial I/O. 2.6.1 Memory map 001816 001916 001A16 001B16 001C16 Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) 003C16 003E16 Interrupt request register 1 (IREQ1) Interrupt control register 1 (ICON1) Fig. 2.6.1 Memory map of registers relevant to serial I/O 2.6.2 Relevant registers Transmit/Receive buffer register b7 b6 b5 b4 b3 b2 b1 b0 Transmit/Receive buffer register (TB/RB) [Address : 18 16] B Function At reset RW 0 The transmission data is written to or the receive data is read out from this buffer register. 1 * At writing: A data is written to the transmit buffer register. * At reading: The contents of the receive buffer register are read out. 2 ? ? ? ? ? ? ? ? 3 4 5 6 7 Note: The contents of transmit buffer register cannot be read out. The data cannot be written to the receive buffer register. Fig. 2.6.2 Structure of Transmit/Receive buffer register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-101 APPLICATION 7540 Group 2.6 Serial I/O1 Serial I/O1 status register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O1 status register (SIO1STS) [Address : 19 16] B (TBE) Name Function 0 : Buffer full 1 : Buffer empty 0 : Buffer empty 1 : Buffer full 0 : Transmit shift in progress 1 : Transmit shift completed At reset RW 0 Transmit buffer empty flag 1 Receive buffer full flag (RBF) 2 Transmit shift register shift completion flag (TSC) 0 0 0 0 0 0 0 1 3 Overrun error flag (OE) 4 5 6 7 0 : No error 1 : Overrun error 0 : No error Parity error flag (PE) 1 : Parity error 0 : No error Framing error flag (FE) 1 : Framing error 0 : (OE) (PE) (FE) = 0 Summing error flag (SE) 1 : (OE) (PE) (FE) = 1 Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "1". Fig. 2.6.3 Structure of Serial I/O1 status register Serial I/O1 control register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O1 control register (SIO1CON) [Address : 1A 16] B Name 0 : f(XIN) 1 : f(XIN)/4 Function At reset RW 0 BRG count source selection bit (CSS) selection bit (SCS) 0 0 1 Serial I/O1 synchronous clock When clock synchronous serial I/O is selected; 0: BRG output divided by 4 1: External clock input When UART is selected; 0: BRG output divided by 16 1: External clock input divided by 16 0: P13 pin 1: SRDY1 output pin 0 : Interrupt when transmit buffer has emptied 1 : Interrupt when transmit shift operation is completed 0 : Transmit disabled 1 : Transmit enabled 0 : Receive disabled 1 : Receive enabled 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O 0: Serial I/O1 disabled 1: Serial I/O1 enabled 2 SRDY1 output enable bit (SRDY) Transmit interrupt 3 source selection bit (TIC) 0 0 4 Transmit enable bit (TE) 5 Receive enable bit (RE) 6 Serial I/O1 mode selection bit (SIOM) 0 0 0 7 Serial I/O1 enable bit (SIOE) 0 Fig. 2.6.4 Structure of Serial I/O1 control register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-102 APPLICATION 7540 Group 2.6 Serial I/O1 UART control register b7 b6 b5 b4 b3 b2 b1 b0 UART control register (UARTCON) [Address : 1B16] B Name Function 0 : 8 bits 1 : 7 bits 0 : Parity checking disabled 1 : Parity checking enabled 0 : Even parity 1 : Odd parity 0 : 1 stop bit 1 : 2 stop bits In output mode 0 : CMOS output 1 : N-channel open-drain output At reset RW 0 Character length selection bit (CHAS) 1 Parity enable bit (PARE) 2 Parity selection bit (PARS) 3 Stop bit length selection bit (STPS) 0 0 0 0 0 4 P11/TxD P-channel output disable bit (POFF) 5 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "1". 1 1 1 6 7 Fig. 2.6.5 Structure of UART control register Baud rate generator b7 b6 b5 b4 b3 b2 b1 b0 Baud rate generator (BRG) [Address : 1C 16] B Function At reset RW 0 Set a count value of baud rate generator. 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? Fig. 2.6.6 Structure of Baud rate generator Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-103 APPLICATION 7540 Group 2.6 Serial I/O1 Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address : 3C 16] B Name Function 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset RW 0 Serial I/O1 receive interrupt request bit 1 Serial I/O1 transmit interrupt request bit 2 INT0 interrupt request bit 3 INT1 interrupt request bit 4 Key-on wake up interrupt request bit 5 CNTR0 interrupt request bit 0 0 0 0 0 0 0 0 6 CNTR1 interrupt request bit 7 Timer X interrupt request bit : These bits can be cleared to "0" by program, but cannot be set to "1". Fig. 2.6.7 Structure of Interrupt request register 1 Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address : 3E 16] B Name Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset RW 0 Serial I/O1 receive interrupt enable bit 1 Serial I/O1 transmit interrupt enable bit 2 INT0 interrupt enable bit 3 INT1 interrupt enable bit 4 Key-on wake up interrupt enable bit 0 0 0 0 0 0 0 0 5 CNTR0 interrupt enable bit 6 CNTR1 interrupt enable bit 7 Timer X interrupt enable bit Fig. 2.6.8 Structure of Interrupt control register 1 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-104 APPLICATION 7540 Group 2.6 Serial I/O1 2.6.3 Serial I/O1 transfer data format Figure 2.6.9 shows the serial I/O1 transfer data format. Clock synchronous serial I/O ST LSB first 1ST-8DATA-1SP LSB MSB SP 1ST-7DATA-1SP ST LSB MSB SP Serial I/O1 1ST-8DATA-1PAR-1SP ST LSB MSB PAR SP 1ST-7DATA-1PAR-1SP ST LSB MSB PAR SP UART 1ST-8DATA-2SP ST LSB MSB 2SP 1ST-7DATA-2SP ST LSB MSB 2SP 1ST-8DATA-1PAR-2SP ST LSB MSB PAR 2SP 1ST-7DATA-1PAR-2SP ST LSB MSB PAR 2SP ST: Start bit SP: Stop bit PAR: Parity bit Fig. 2.6.9 Serial I/O1 transfer data format Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-105 APPLICATION 7540 Group 2.6 Serial I/O1 2.6.4 Application example of clock synchronous serial I/O1 For clock synchronous serial I/O1, the transmitter and the receiver use the same clock. Synchronizing with this clock, the transmit operation of the transmitter and the receive operation of the receiver are executed at the same time. If an internal clock is used as the operation clock, transfer is started by a write signal to the TB/RB. (1) Data transfer rate The synchronous clock frequency is calculated by the following formula; q When the internal clock is selected (when baud rate generator is used) f(XIN) Division ratio * 1 (BRG setting value * 2 + 1) 4 Synchronous clock frequency [Hz] = Division ratio*1 : "1" or "4" is selected (set by bit 0 of serial I/O1 control register) BRG setting value* 2 : 0 to 255 (0016 to FF16) is set q When the external clock is selected Synchronous clock frequency [Hz] = Clock input to SCLK1 pin Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-106 APPLICATION 7540 Group 2.6 Serial I/O1 (2) Clock synchronous serial I/O setting method Figure 2.6.10 and Figure 2.6.11 show the setting method for the clock synchronous serial I/O1. Process 1: Stop and initialize serial I/O. b7 b0 00 Serial I/O1 control register (SIO1CON) [Address 1A16] Transmit operation stop and initialized Receive operation stop and initialized Process 2: Disable serial I/O1 transmit/receive interrupt. b7 b0 00 Interrupt control register 1 (ICON1) [Address 3E16] Serial I/O1 receive interrupt disabled Serial I/O1 transmit interrupt disabled Process 3: Set serial I/O1 control register. b7 b0 11 Serial I/O1 control register (SIO1CON) [Address 1A16] BRG count source selected (set in internal clock selected) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronous clock selected 0: BRG output/4 (Note 1) 1: External clock input SRDY1 output enable selected 0: P13 pin operates as normal I/O pin 1: P13 pin operates as SRDY1 output pin (Note 2) Transmit interrupt source selected 0: When transmit buffer has emptied 1: When transmit shift operation is completed Transmit enable selected 0: Transmit disabled (at half-duplex communication receive) 1: Transmit enabled (at full-duplex communication) (Note 3) Receive enable selected 0: Receive disabled (at half-duplex communication transmit) 1: Receive enabled (at full-duplex communication) (Note 3) Clock synchronous serial I/O Serial I/O1 enabled (P10-P13 pins operate as serial I/O1 pins) Notes 1: Setting of serial I/O1 synchronous selection bit is as follows: "0": P12 pin is set to be an output pin of the synchronous clock. "1": P12 pin is set to be an input pin of the synchronous clock. 2: When an external clock input is selected as the synchronous clock, and the receiver performs the SRDY1 output, set "1" to the transmit enable bit in addition to the receive enable bit and SRDY1 output enable bit. 3: When data transmission is executed at the state that an external clock input is selected as the synchronous clock, set "1" to the transmit enable bit while the SCLK1 is "H" state. Process 4: When BRG output/4 is selected as synchronous clock, set value to baud rate generator. Baud rate generator (BRG) [Address 1C16] Set baud rate value Fig. 2.6.10 Setting method for clock synchronous serial I/O1 (1) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-107 APPLICATION 7540 Group 2.6 Serial I/O1 Process 5: In order not to execute the no requested interrupt processing, set "0" (no requested) to the serial I/O1 transmit/receive interrupt request bit. b7 b0 00 Interrupt request register 1 (IREQ1) [Address 3C16] No serial I/O1 receive interrupt request issued No serial I/O1 transmit interrupt request issued Process 6: When the interrupt is used, set "1" (interrupt enabled) to the serial I/O transmit/receive interrupt enable bit. b7 b0 11 Interrupt control register 1 (ICON1) [Address 3E16] Serial I/O1 receive interrupt enabled Serial I/O1 transmit interrupt enabled Process 7: Transmit/Receive of serial data (Notes 1, 2). Transmit/Receive buffer register (TB/RB) [Address 1816] Set transmit data (in full-duplex communication) Set dummy data (in half-duplex communication) Notes 1: When data transmission is executed at the state that an external clock input is selected as the synchronous clock, set the transmit data while the SCLK is "H" state. 2: When inputting the SRDY1 signal, set used pins to to the input mode before transmitting data. Fig. 2.6.11 Setting method for clock synchronous serial I/O1 (2) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-108 APPLICATION 7540 Group 2.6 Serial I/O1 (3) Communication using clock synchronous serial I/O1 (transmit/receive) Outline : 2-byte data is transmitted and received, using the clock synchronous serial I/O1. SRDY1 signal is used for communication control. Specifications : *The serial I/O1 (clock synchronous serial I/O selected ) is used. *Synchronous clock frequency : 125 kHz; f(XIN) = 4 MHz divided by 32 *The receiver outputs the SRDY1 signal at 2 ms intervals which the timer generates, and 2-byte data is transferred from the transmitter to the receiver. Figure 2.6.12 shows a connection diagram, Figure 2.6.13 shows a timing chart, Figure 2.6.14 shows the control procedure of transmitter, and Figure 2.6.15 shows an example of control procedure of receiver. Transmitter P37/INT0 SCLK1 TXD1 Receiver SRDY1 SCLK1 RXD1 7540 Group 7540 Group Fig. 2.6.12 Connection diagram SRDY1 SCLK1 TXD D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 ..... ..... ..... 2ms Fig. 2.6.13 Timing chart Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-109 APPLICATION 7540 Group 2.6 Serial I/O1 RESET Initialization SEI CLD CLT Set serial I/O1 control register 1 1 0 1 0 0 0 0 SIO1CON(Address 1A16) BRG count source: f(XIN) Synchronous clock: BRG output/4 P13 pin (Normal I/O pin) Transmit interrupt source: W h e n tra n s m it b u ff e r h a s e m p tie d Transmit enabled Receive disabled Clock synchronous serial I/O Serial I/O1 enabled Set baud rate generator "0716" BRG(Address 1C16) Set INT0 interrupt active edge 0 INTEDGE(Address 3A16) INT0 falling edge active N INT0 falling edge input? Y Write the first-byte transmission data to the transmit/receive buffer register TB/RB(Address 1816) Transmit buffer has emptied? (checked by b0 of SIO1STS (address 1916)) Y Write the second-byte transmission data to the transmit/receive buffer register TB/RB(Address 1816) N Transmit buffer has emptied? (checked by b0 of SIO1STS (address 1916)) Y N Transmit shift has completed? (checked by b2 of SIO1STS (address 1916)) Y N Fig. 2.6.14 Control procedure of transmitter Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-110 APPLICATION 7540 Group 2.6 Serial I/O1 RESET Initialization SEI CLD CLT Set serial I/O1 control register 1111 11 SIO1CON(Address 1A16) Synchronous clock: External clock input SRDY1 output pin Transmit enabled Receive enabled Clock synchronous serial I/O Serial I/O enabled 2 ms elapsed ? (generated by timer) Y Set dummy data to the transmit/receive buffer TB/RB(Address 1816) N Receive buffer is full? (checked by b1 of SIO1STS (address 1916)) Y Read the first-byte reception data from the transmit/receive buffer register TB/RB(Address 1816) N Receive buffer is full? (checked by b1 of SIO1STS (address 1916)) Y N Read the second-byte reception data from the transmit/receive buffer register TB/RB(Address 1816) Fig. 2.6.15 Control procedure of receiver Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-111 APPLICATION 7540 Group 2.6 Serial I/O1 2.6.5 Application example of clock asynchronous serial I/O1 For clock asynchronous serial I/O1 (UART), the transfer formats used by a transmitter and receiver must be identical. In the 7540 Group, eight serial data transfer formats can be selected. (1) Data transfer rate The transfer bit rate is calculated by the following formula; q When the internal clock is selected (when baud rate generator is used) f(XIN) (BRG setting value Transfer bit rate [bps] = Division ratio *1 *2 + 1) 16 Division ratio*1 : "1" or "4" is selected (set by bit 0 of serial I/O1 control register) BRG setting value* 2 : 0 to 255 (0016 to FF16) is set q When the external clock is selected Transfer bit rate [bps] = Clock input to SCLK1 pin/16 Table 2.6.1 shows the setting example of baud rate generator and transfer bit rate values. Table 2.6.1 Setting example of baud rate generator (BRG) and transfer bit rate values BRG count source f(XIN) / 4 f(XIN) / 4 f(XIN) / 4 f(XIN) / 4 f(XIN) / 4 f(XIN) / 4 f(XIN) / 4 f(XIN) / 4 f(XIN) f(XIN) f(XIN) BRG set value 255 (FF16) 127 (7F16) 63 (3F16) 31 (1F16) 15 (0F16) 7 (0716) 3 (0316) 1 (0116) 3 (0316) 1 (0116) 0 (0016) Transfer bit rate (bps) At f(XIN) = 4.9152 MHz At f(XIN) = 8 MHz 300 600 1200 2400 4800 9600 19200 38400 76800 153600 307200 488.28125 976.5625 1953.125 3906.25 7812.5 15625 31250 62500 125000 250000 500000 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-112 APPLICATION 7540 Group 2.6 Serial I/O1 (2) UART setting method Figure 2.6.16 and Figure 2.6.17 show the setting method for UART of serial I/O1. Process 1: Stop and initialize serial I/O. b7 b0 00 Serial I/O1 control register (SIO1CON) [Address 1A16] Transmit operation stop and initialization Receive operation stop and initialization Process 2: Disable serial I/O1 transmit/receive interrupt. b7 b0 00 Interrupt control register 1 (ICON1) [Address 3E16] Serial I/O1 receive interrupt disabled Serial I/O1 transmit interrupt disabled Process 3: Set serial I/O1 control register. b7 b0 10 Serial I/O1 control register (SIO1CON) [Address 1A16] BRG count source selected (set in internal clock selected) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronous clock selected (Note 1) 0: BRG output/16 1: External clock input/16 Transmit interrupt source selected 0: When transmit buffer has emptied 1: When transmit shift operation is completed Transmit enable selected 0: Transmit disabled (at half-duplex communication receive) 1: Transmit enabled (at full-duplex communication) (Note 2) Receive enable selected 0: Receive disabled (at half-duplex communication transmit) 1: Receive enabled (at full-duplex communication) (Note 2) Clock asynchronous serial I/O Serial I/O1 enabled (P10-P12 pins operate as serial I/O1 pins)(Note 3) Note 1: Setting of serial I/O1 synchronous clock selection bit is as follows; "0": P12 pin can be used as a normal I/O pin "1": P12 pin is used as an input pin for an external clock. 2: When data transmission is executed at the state that an external clock input is selected as the synchronous clock, set "1" to the transmit enable bit while the SCLK1 is "H" state. 3: When clock asynchronous (UART) serial I/O is selected, P13 pin can be used as a normal I/O pin. Fig. 2.6.16 Setting method for UART of serial I/O1 (1) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-113 APPLICATION 7540 Group 2.6 Serial I/O1 Process 4: Set UART control register. b7 b0 UART control register (UARTCON) [Address 1B16] Select character length 0: 8 bits 1: 7 bits Select parity enable 0: Parity disabled 1: Parity enabled Select parity (valid only when parity is enabled) 0: Even parity 1: Odd parity Select stop bit length 0: 1 stop bit 1: 2 stop bits Select P11/TxD P-channel output disable (in output mode) 0: CMOS output 1: N-channel open-drain output Process 5: When BRG output/16 is selected as synchronous clock, set value to baud rate generator. Baud rate generator (BRG) [Address 1C16] Set baud rate value Process 6: In order not to execute the no requested interrupt processing, set "0" (no requested) to the serial I/O1 transmit/receive interrupt request bit. b7 b0 00 Interrupt request register 1 (IREQ1) [Address 3C16] No serial I/O1 receive interrupt request issued No serial I/O1 transmit interrupt request issued Process 7: When the interrupt is used, set "1" (interrupt enabled) to the serial I/O1 transmit/receive interrupt enable bit. b7 b0 11 Interrupt control register 1 (ICON1) [Address 3E16] Serial I/O1 receive interrupt enabled Serial I/O1 transmit interrupt enabled Process 8: When transmitting, start serial data transmission (Note). Transmit/Receive buffer register (TB/RB) [Address 1816] Set transmit data Note: When data transmission is executed at the state that an external clock input is selected as the synchronous clock, set the transmit data while the SCLK1 is "H" state. Fig. 2.6.17 Setting method for UART of serial I/O1 (2) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-114 APPLICATION 7540 Group 2.6 Serial I/O1 (3) Communication using UART of serial I/O (transmit/receive) Outline : 2-byte data is transmitted and received, using UART. Port P00 is used for communication control. Specifications : *The Serial I/O1 (UART selected ) is used. *Transfer bit rate : 9600 bps (f(XIN) = 4.9152 MHz divided by 512) *Communication control using port P00 (output level of port P00 is controlled by software) 2-byte data is transferred from the transmitter to the receiver at 10 ms intervals which the timer generates. Figure 2.6.18 shows a connection diagram, Figure 2.6.19 shows a timing chart, Figure 2.6.20 shows the control procedure of transmitter, and Figure 2.6.21 shows an example of control procedure of receiver. Transmitter P00 TxD Receiver P00 RXD 7540 Group 7540 Group Fig. 2.6.18 Connection diagram P00 ..... TXD ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2) ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2) ST D0 ..... 10 ms Fig. 2.6.19 Timing chart Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-115 APPLICATION 7540 Group 2.6 Serial I/O1 RESET Initialization SEI CLD CLT Set serial I/O1 control register 10010 01 SIO1CON(Address 1A16) BRG count source: f(XIN)/4 Synchronous clock: BRG output/16 Transmit interrupt source: W h e n tra n s m it b u ff e r h a s e m p tie d Transmit enabled Receive disabled UART Serial I/O1 enabled Set UART control register 01 0 0 UARTCON(Address 1B16) Character length: 8 bits Parity disabled Stop bit length: 2 bits TXD: CMOS output Set baud rate generator "0716" BRG(Address 1C16) Set the communication control port P00 to the output mode. 10 ms elapsed ? (generated by timer) Y Set "1" to the communication control port P00. N Write the first-byte transmission data to the transmit/receive buffer register TB/RB(Address 1816) Transmit buffer has emptied? (checked by b0 of SIO1STS (address 1916)) Y Write the second-byte transmission data to the transmit/receive buffer register TB/RB(Address 1816) N Transmit buffer has emptied? (checked by b0 of SIO1STS (address 1916)) Y N Transmit shift has completed? (checked by b2 of SIO1STS (address 1916)) Y Set "0" to the communication control port P00. N Fig. 2.6.20 Control procedure of transmitter Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-116 APPLICATION 7540 Group 2.6 Serial I/O1 Initialization SEI CLD CLT Set serial I/O1 control register 1010 01 SIO1CON(Address 1A16) BRG count source: f(XIN)/4 Synchronous clock: BRG output/16 Transmit disabled Receive enabled UART Serial I/O1 enabled Set UART control register 1 0 0 UAR TCON(Address 1B16) Character length: 8 bits Parity disabled Stop bit length: 2 bits Set baud rate generator "0716" BRG(Address 1C16) Set the communication control port P00 to the input mode. Receive buffer is full? (checked by b1 of SIO1STS (address 1916)) Y Read the first-byte transmission data from the transmit/receive buffer register TB/RB(Address 1816) N Error occurs? (checked by b6 of SIO1STS (address 1916)) N Y Receive buffer is full? (checked by b1 of SIO1STS (address 1916)) Y Read the second-byte transmission data from the transmit/receive buffer register TB/RB(Address 1816) N Error occurs? (checked by b6 of SIO1STS (address 1916)) N Y Error processing N Communication control port P00 = "0" ? Y Fig. 2.6.21 Control procedure of receiver Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-117 APPLICATION 7540 Group 2.6 Serial I/O1 2.6.6 Notes on Serial I/O1 Notes on using serial I/O1 are described below. (1) Notes when selecting clock synchronous serial I/O When the clock synchronous serial I/O1 is used, serial I/O2 cannot be used. When the transmit operation is stopped, clear the serial I/O1 enable bit and the transmit enable bit to "0" (serial I/O1 and transmit disabled). q Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to "0" (serial I/O1 disabled), the internal transmission is running (in this case, since pins TxD1, RxD1, SCLK1, and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to "1" at this time, the data during internally shifting is output to the TxD1 pin and an operation failure occurs. When the receive operation is stopped, clear the receive enable bit to "0" (receive disabled), or clear the serial I/O1 enable bit to "0" (serial I/O1 disabled). When the transmit/receive operation is stopped, clear both the transmit enable bit and receive enable bit to "0" (transmit and receive disabled) simultaneously. (any one of data transmission and reception cannot be stopped.) q Reason In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to "0" (transmit disabled). Also, the transmission circuit cannot be initialized even if the serial I/O1 enable bit is cleared to "0" (serial I/O1 disabled) (same as ). When signals are output from the SRDY1 pin on the reception side by using an external clock, set all of the receive enable bit, the SRDY1 output enable bit, and the transmit enable bit to "1". When the SRDY1 signal input is used, set the using pin to the input mode before data is written to the transmit/receive buffer register. Setup of a selected; "0" : P12 "1" : P12 Setup of a "0" : P13 "1" : P13 serial I/O1 synchronous clock selection bit when a clock synchronous serial I/O is pin turns into an output pin of a synchronous clock. pin turns into an input pin of a synchronous clock. SRDY1 output enable bit (SRDY1) when a clock synchronous serial I/O1 is selected; pin can be used as a normal I/O pin. pin turns into a SRDY1 output pin. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-118 APPLICATION 7540 Group 2.6 Serial I/O1 (2) Notes when selecting UART When the clock asynchronous serial I/O1 (UART) is used, serial I/O2 can be used only when BRG output divided by 16 is selected as the synchronous clock. When the transmit operation is stopped, clear the transmit enable bit to "0" (transmit disabled). q Reason Same as (1) . When the receive operation is stopped, clear the receive enable bit to "0" (receive disabled). When the transmit/receive operation is stopped, clear the transmit enable bit to "0" (transmit disabled) and receive enable bit to "0" (receive disabled). Setup of a serial I/O1 synchronous clock selection bit when a clock asynchronous (UART) serial I/O is selected; "0": P12 pin can be used as a normal I/O pin. "1": P12 pin turns into an input pin of an external clock. When clock asynchronous (UART) type serial I/O is selected, it is P13 pin. It can be used as a normal I/O pin. (3) Notes common to clock synchronous serial I/O and UART Set the serial I/O control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to "0." The transmit shift completion flag changes from "1" to "0" with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. Clear both the transmit enable bit (TE) and the receive enable bit (RE) to "0" Set the bits 0 to 3 and bit 6 of the serial I/O1 control register Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to "1" Fig. 2.6.22 Sequence of setting serial I/O1 control register again When data transmission is executed at the state that an external clock input is selected as the synchronous clock, set "1" to the transmit enable bit while the SCLK1 is "H" state. Also, write to the transmit buffer register while the SCLK1 is "H" state. When the transmit interrupt is used, set as the following sequence. Serial I/O1 transmit interrupt enable bit is set to "0" (disabled). Serial I/O1 transmit enable bit is set to "1". Serial I/O1 transmit interrupt request bit is set to "0". Serial I/O1 transmit interrupt enable bit is set to "1" (enabled). q Reason When the transmit enable bit is set to "1", the transmit buffer empty flag and transmit shift completion flag are set to "1". Accordingly, even if the timing when any of the above flags is set to "1" is selected for the transmit interrupt source, interrupt request occurs and the transmit interrupt request bit is set. Write to the baud rate generator (BRG) while the transmit/receive operation is stopped. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z Can be set with the LDM instruction at the same time 2-119 APPLICATION 7540 Group 2.7 Serial I/O2 2.7 Serial I/O2 This paragraph explains the registers setting method and the notes relevant to the serial I/O. 2.7.1 Memory map 000316 003016 003116 003D16 003F16 Port P1 direction register (P1D) Serial I/O2 control register (SIO2CON) Serial I/O2 register (SIO2) Interrupt request register 2 (IREQ2) Interrupt control register 2 (ICON2) Fig. 2.7.1 Memory map of registers relevant to serial I/O2 2.7.2 Relevant registers Port P1 direction register b7 b6 b5 b4 b3 b2 b1 b0 Port P1 direction register (P1D) [Address : 03 16] B Name Function 0 : Port P10 input mode 1 : Port P10 output mode 0 : Port P11 input mode 1 : Port P11 output mode 0 : Port P12 input mode 1 : Port P12 output mode 0 : Port P13 input mode 1 : Port P13 output mode 0 : Port P14 input mode 1 : Port P14 output mode At reset RW 0 Port P1 direction register 1 2 3 4 0 0 0 0 0 ? ? ? 5 Nothing is allocated for these bits. When these bits are read out, the values are undefined. 6 7 Fig. 2.7.2 Structure of Port P1 direction register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-120 APPLICATION 7540 Group 2.7 Serial I/O2 Serial I/O2 control register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O2 control register (SIO2CON) [Address : 3016] B Name b2 b1 b0 Function At reset RW 0 Internal synchronous clock selection bits 1 2 3 4 5 6 7 0 0 0 : f(XIN)/8 0 0 1 : f(XIN)/16 0 1 0 : f(XIN)/32 0 1 1 : f(XIN)/64 1 1 0 : f(XIN)/128 1 1 1 : f(XIN)/256 SDATA2 pin selection bit 0 : I/O port / SDATA2 input (Note) 1 : SDATA2 output Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "0". Transfer direction selection bit 0 : LSB first 1 : MSB first 0 : External clock (SCLK2 is input) SCLK2 pin selection bit 1 : Internal clock (SCLK2 is output) Transmit / receive shift 0 : shift in progress completion flag 1 : shift completed 0 0 0 0 0 0 0 0 Note: When using it as a SDATA input, set the port P13 direction register bit to "0". Fig. 2.7.3 Structure of Serial I/O2 control register Serial I/O2 register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O2 register (SIO2) [Address : 31 16] B Function * At transmitting : Set a transmission data. * At receiving : A reception data is stored. At reset RW 0 A shift register for serial transmission and reception. 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? Fig. 2.7.4 Structure of Serial I/O2 register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-121 APPLICATION 7540 Group 2.7 Serial I/O2 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2) [Address : 3D 16] B Name Function 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset RW 0 Timer Y interrupt request bit 1 Timer Z interrupt request bit 2 Timer A interrupt request bit 3 Serial I/O2 interrupt request bit 4 AD converter interrupt request bit 0 0 0 0 0 0 0 0 5 Timer 1 interrupt request bit 6 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 7 : These bits can be cleared to "0" by program, but cannot be set to "1". Fig. 2.7.5 Structure of Interrupt request register 2 Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 2 (ICON2) [Address : 3F 16] B Name Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset RW 0 Timer Y interrupt enable bit 1 Timer Z interrupt enable bit 2 Timer A interrupt enable bit 3 Serial I/O2 interrupt enable bit 4 AD conversion interrupt enable bit 5 Timer 1 interrupt enable bit 0 0 0 0 0 0 0 0 6 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 7 Fig. 2.7.6 Structure of Interrupt control register 2 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-122 APPLICATION 7540 Group 2.7 Serial I/O2 2.7.3 Application example of serial I/O2 (1) Serial I/O2 setting method Figure 2.7.7 and Figure 2.7.8 show the setting method for the serial I/O2. Process 1: Disable serial I/O2 transmit/receive interrupt. b7 b0 0 Interrupt control register 2 (ICON2) [Address 3F16] Serial I/O2 interrupt disabled Process 2: Set port P1 according to the usage condition. b7 b0 Port P1 direction register (P1D) [Address 0316] P12/SCLK2 pin (Note 1) P13/SDATA2 pin (Notes 2, 3) Notes 1: When an external clock input is selected, set P12/SCLK2 pin to the input mode. 2: When P13/SDATA2 pin is used as the P13 pin, set this bit to "0". 3: When this bit is set to "0" at transmit and the internal clock is selected for SCLK2, the SDATA2 pin is in a high impedance state after the data transfer is completed. Process 3: Set serial I/O2 control register. b7 b0 Serial I/O2 control register (SIO2CON) [Address 3016] Internal synchronous clock selected (set in internal clock selected) b2b1b0 0 0 0: f(XIN)/8 0 0 1: f(XIN)/16 0 1 0: f(XIN)/32 0 1 1: f(XIN)/64 1 1 0: f(XIN)/128 1 1 1: f(XIN)/256 SDATA2 pin selected 0: I/O port/SDATA2 input (at receive) 1: SDATA2 output (at transmit) Transfer direction selected 0: LSB first 1: MSB first SCLK2 pin selected 0: External clock (SCLK2 is input) 1: Internal clock (SCLK2 is outpu) Process 4: In order not to execute the no requested interrupt processing, set "0" (no requested) to the serial I/O2 interrupt request bit. b7 b0 0 Interrupt request register 2 (IREQ2) [Address 3D16] No serial I/O2 interrupt request issued Fig. 2.7.7 Setting method for serial I/O2 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-123 APPLICATION 7540 Group 2.7 Serial I/O2 Process 5: When the interrupt is used, set "1" (interrupt enabled) to the serial I/O2 interrupt. enable bit. b7 b0 1 Interrupt control register 2 (ICON2) [Address 3F16] Serial I/O2 interrupt enabled Process 6: When transmitting, start serial data transmission. Serial I/O2 register (SIO2) [Address 3116] Set transmit data Fig. 2.7.8 Setting method for serial I/O2 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-124 APPLICATION 7540 Group 2.7 Serial I/O2 (2) Communication using serial I/O2 (transmit/receive) Outline: 2-byte data is transmitted and received, using the serial I/O2. Port P00 is used for communication control and outputs the quasi-SRDY signal. Specifications: * The serial I/O2, clock synchronous serial I/O, is used. * Synchronous clock frequency : 125 kHz; f(XIN) = 8 MHz divided by 64 * Transfer direction : LSB first * The receiver outputs the quasi-SRDY signal at 2 ms intervals which the timer generates, and 2-byte data is transferred from the transmitter to the receiver. Figure 2.7.9 shows a connection diagram, Figure 2.7.10 shows a timing chart, Figure 2.7.11 shows the control procedure of transmitter, and Figure 2.7.12 shows an example of control procedure of receiver. Transmitter P37/INT0 SCLK SDATA Receiver P00 SCLK SDATA 7540 Group 7540 Group Fig. 2.7.9 Connection diagram Quasi-SRDY SCLK SDATA D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 ..... ..... ..... 2 ms Fig. 2.7.10 Timing chart Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-125 APPLICATION 7540 Group 2.7 Serial I/O2 RESET Initialization SEI CLD CLT Set port P12 to the output mode. Set port P13 to the output mode. (Note) Set serial I/O2 control register 10 1011 SIO2CON(Address 3016) Synchronous clock: f(XIN)/64 SDATA2 pin: SDATA2 output LSB first SCLK2 pin: Internal clock Set INT0 interrupt active edge 0 INTEDGE(Address 3A16) INT0 falling edge active N INT0 falling edge input? Y Set "0" to the serial I/O2 interrupt request bit. Write the first-byte transmission data to the serial I/O2 register SIO2(Address 3116) Transmit shift has completed? (checked by serial I/O2 interrupt request bit) Y Set "0" to the serial I/O2 interrupt request bit. Write the second-byte transmission data to the serial I/O2 register SIO2(Address 3116) N Transmit shift has completed? (checked by serial I/O2 interrupt request bit) Y N Note: When direction register of P13/SDATA2 pin is set to the input mode and the internal clock is selected, the SDATA2 pin is in a high impedance state after the data transfer is completed. Fig. 2.7.11 Control procedure of transmission side Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-126 APPLICATION 7540 Group 2.7 Serial I/O2 RESET Initialization SEI CLD CLT Set quasi-SRDY signal port P00 to the output mode. Output "1" from quasi-SRDY signal port P00. Set port P12 to the input mode. Set port P13 to the input mode. Set serial I/O2 control register 00 0011 SIO2CON(Address 3016) Synchronous clock: f(XIN)/64 SDATA2 pin: SDATA2 input LSB first SCLK2 pin: External clock 2 ms elapsed ? (generated by timer) Y Output "0" from quasi-SRDY signal port P00. Output "1" from quasi-SRDY signal port P00. Set dummy data to the serial I/O2 register (Note 1) SIO2(Address 3116) N Receive has completed? (checked by b7 of SIO2CON (address 3016)) Y Wait for half cycle of clock (Note 2) Read receive data from serial I/O2 register SIO2(Address 3116) Set dummy data to serial I/O2 register (Note 1) SIO2(Address 3116) N Receive has completed? (checked by b7 of SIO2CON (address 3016)) Y Wait for half cycle of clock (Note 2) Read receive data from serial I/O2 register SIO2(Address 3116) N Notes 1: The transmit/receive shift completion flag of the serial I/O2 control register is "1" after transmit/receive shift is completed. In order to set "0" to this flag, set data (dummy data at receive) to the serial I/O2 register by program. 2: Bit 7 (transmit/receive shift completion flag) of the serial I/O2 control register is set earlier than the completion of the actual shift operation for a half cycle of shift clock. Accordingly, when the shift completion is checked by using this bit, read/write the serial I/O2 register after a half or more cycle of clock from the setting "1" to this bit is checked. Fig. 2.7.12 Control procedure of reception side Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-127 APPLICATION 7540 Group 2.7 Serial I/O2 2.7.4 Notes on serial I/O2 Notes on using serial I/O2 are described below. (1) Note on serial I/O1 Serial I/O2 can be used only when serial I/O1 is not used or serial I/O1 is used as UART and the BRG output divided by 16 is selected as the synchronous clock. (2) Note on SCLK2 pin When an external clock is selected, set "0" to bit 2 of the port P1 direction register (input mode). (3) Note on SDATA2 pin When P13/SRDY1/SDATA2 pin is used as the SDATA input, set "0" to bit 3 of the port P1 direction register (input mode). When the internal clock is selected as the transfer and P13/SDATA2 pin is set to the input mode, the SDATA2 pin is in a high-impedance state after the data transfer is completed. (4) Notes on serial I/O2 transmit/receive shift completion flag The transmit/receive shift completion flag of the serial I/O2 control register is "1" after transmit/ receive shift is completed. In order to set "0" to this flag, set data (dummy data at receive) to the serial I/O2 register by program. Bit 7 (transmit/receive shift completion flag) of the serial I/O2 control register is set earlier than the completion of the actual shift operation for a half cycle of shift clock. Accordingly, when the shift completion is checked by using this bit, read/write the serial I/O2 register after a half or more cycle of clock from the setting "1" to this bit is checked. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-128 APPLICATION 7540 Group 2.8 A/D converter 2.8 A/D converter This paragraph explains the registers setting method and the notes relevant to the A/D converter. 2.8.1 Memory map 003416 003516 003616 A/D control register (ADCON) A/D conversion register (low-order) (ADL) A/D conversion register (high-order) (ADH) 003D16 Interrupt request register 2 (IREQ2) 003F16 Interrupt control register 2 (ICON2) Fig. 2.8.1 Memory map of registers relevant to A/D converter 2.8.2 Relevant registers A/D control register b7 b6 b5 b4 b3 b2 b1 b0 A/D control register (ADCON) [Address : 3416] B 0 1 2 3 4 5 6 7 Name Analog input pin selection bits b2 b1 b0 Function 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : P20/AN0 1 : P21/AN1 0 : P22/AN2 1 : P23/AN3 0 : P24/AN4 1 : P25/AN5 0 : P26/AN6 1 : P27/AN7 At reset RW 0 0 (Note) (Note) 0 0 1 0 0 0 Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "0". AD conversion completion bit 0 : Conversion in progress 1 : Conversion completed Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". Note: These can be used only for the 36-pin package versions. : This bit can be cleared to "0" by program, but cannot be set to "1". Fig. 2.8.2 Structure of A/D control register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-129 APPLICATION 7540 Group 2.8 A/D converter A/D conversion register (low-order) b7 b6 b5 b4 b3 b2 b1 b0 A/D conversion register (low-order) (ADL) [Address : 3516] B stored. Function At reset RW 0 The read-only register in which the A/D conversion's results are 1 2 3 4 b7 b7 < 8-bit read> b0 ? ? ? ? ? b9 b8 b7 b6 b5 b4 b3 b2 < 10-bit read> b0 5 6 7 b7 b6 b5 b4 b3 b2 b1 b0 ? ? ? Fig. 2.8.3 Structure of A/D conversion register (low-order) A/D conversion register (high-order) b7 b6 b5 b4 b3 b2 b1 b0 A/D conversion register (high-order) (ADH) [Address : 3616] B stored. Function At reset RW 0 The read-only register in which the A/D conversion's results are 1 b7 < 10-bit read> b0 b9 b8 ? ? ? ? ? ? ? ? 2 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 3 4 5 6 7 Fig. 2.8.4 Structure of A/D conversion register (high-order) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-130 APPLICATION 7540 Group 2.8 A/D converter Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2) [Address : 3D 16] B Name Function 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset RW 0 Timer Y interrupt request bit 1 Timer Z interrupt request bit 2 Timer A interrupt request bit 3 Serial I/O2 interrupt request bit 4 AD converter interrupt request bit 0 0 0 0 0 0 0 0 5 Timer 1 interrupt request bit 6 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 7 : These bits can be cleared to "0" by program, but cannot be set to "1". Fig. 2.8.5 Structure of Interrupt request register 2 Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 2 (ICON2) [Address : 3F 16] B Name Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset RW 0 Timer Y interrupt enable bit 1 Timer Z interrupt enable bit 2 Timer A interrupt enable bit 3 Serial I/O2 interrupt enable bit 4 AD conversion interrupt enable bit 5 Timer 1 interrupt enable bit 0 0 0 0 0 0 0 0 6 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 7 Fig. 2.8.6 Structure of Interrupt control register 2 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-131 APPLICATION 7540 Group 2.8 A/D converter 2.8.3 A/D converter application examples (1) Setting of A/D converter Figure 2.8.7 shows the relevant registers setting. Process 1: Disable A/D conversion interrupt. b7 b0 0 Interrupt control register 2 (ICON2) [Address 3F16] A/D conversion interrupt disabled Process 2: Set A/D control register. b7 b0 A/D control register (ADCON) [Address 3416] Analog input pins selected b2b1b 0 00 00 01 01 10 10 11 11 0: P20/AN0 1: P21/AN1 0: P22/AN2 1: P23/AN3 0: P24/AN4 1: P25/AN5 0: P26/AN6 (Note) 1: P27/AN7 (Note) Note: These can be used only for 36-pin version. Process 3: In order not to execute the no requested interrupt processing, set "0" (no requested) to the A/D conversion interrupt request bit. b7 b0 0 Interrupt request register 2 (IREQ2) [Address 3D16] No A/D conversion interrupt request issued Process 4: When the interrupt is used, set "1" (interrupt enabled) to the A/D conversion interrupt enable bit. b7 b0 1 Interrupt control register 2 (ICON2) [Address 3F16] A/D conversion interrupt enabled Process 5: Start A/D conversion. b7 b0 0 A/D control register (ADCON) [Address 3416] Start A/D conversion Fig. 2.8.7 Relevant registers setting Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-132 APPLICATION 7540 Group 2.8 A/D converter (2) Control procedure Outline : The analog input voltage input from a sensor is converted to digital values. Specifications : *The analog input voltage input from a sensor is converted to digital values. *P20/AN0 pin is used as an analog input pin. Figure 2.8.8 shows a connection diagram, and Figure 2.8.9 shows an example of control procedure. P20/AN0 Sensor 7540 Group Fig. 2.8.8 Connection diagram A/D conversion processing Set "0" to the A/D conversion interrupt enable bit. (A/D conversion interrupt disabled) Set analog input pins 1 0 0 0 ADCON(Address 3416) Analog input pins: P20/AN0 Set "0" to the A/D conversion interrupt request bit. Set "1" to the A/D conversion interrupt enable bit. (A/D conversion interrupt enabled) (Note 1) Start A/D conversion 0 0 0 0 ADCON(Address 3416) Start A/D conversion N A/D conversion completed ? (Note 2) Y Read ADH (address 3616) (Note 3) Read ADL (address 3516) (Note 4) RTS Notes 1: In this case, the A/D conversion interrupt is used. 2: The completion of the A/D conversion is checked by the following; * The A/D conversion completion bit of the A/D control register is "1". * The A/D conversion interrupt request bit of the interrupt request register 2 is "1". * Branch to the A/D conversion interrupt processing routine is executed. (In this time, the A/D conversion interrupt is enabled.) 3: At 10-bit read: the conversion result of the high-order 2 bits (b9, b8) can be read. At 8-bit read: Not used. 4: At 10-bit read: the conversion result of the low-order 8 bits (b7 to b0) can be read. At 8-bit read: the conversion result of b7 to b0 can be read. Fig. 2.8.9 Control procedure Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-133 APPLICATION 7540 Group 2.8 A/D converter 2.8.4 Notes on A/D converter Notes on A/D converter are described below. (1) Analog input pin Figure 2.8.10 shows the internal equivalent circuit of an analog input. In order to execute the A/D conversion correctly, to complete the charge to an internal capacitor within the specified time is required. The maximum output impedance of the analog input source required to complete the charge to a capacitor within the specified time is as follows; About 35 k (at f(XIN) = 8 MHz) When the maximum output impedance exceeds the above value, equip an analog input pin with an external capacitor of 0.01F to 1F between an analog input pin and VSS. Further, be sure to verify the operation of application products on the user side. q Reason An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when signals from signal source with high impedance are input to an analog input pin, charge and discharge noise generates. This may cause the A/D conversion/comparison precision to be worse. VCC (Note 1) R 1.5 k(Typical) ANi (i=0 to 7: 36-pin version i=0 to 5: 32-pin version) C2 1.5 pF(Typical) SW1 (Note 2) (Note 1) Typical voltage generation circuit Switch tree, ladder resistor Chopper Amp. C1 12 pF(Typical) VSS VSS Notes 1: This is a parasitic diode. 2: Only the selected analog input pin is turned on. A/D control circuit VSS VREF Fig. 2.8.10 Connection diagram (2) Clock frequency during A/D conversion The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is too low. Thus, make sure the following during an A/D conversion. * f(XIN) is 500 kHz or more * Do not execute the STP instruction (3) Note on A/D converter As for AD translation accuracy, on the following operating conditions, accuracy may become low. (1) Since the analog circuit inside a microcomputer becomes sensitive to noise when VREF voltage is set up lower than Vcc voltage, accuracy may become low rather than the case where VREF voltage and Vcc voltage are set up to the same value. (2) When VREF voltage is lower than [3.0 V], the accuracy at the low temperature may become extremely low compared with that at room temperature When the system would be used at low temperature, the use at VREF=3.0 V or more is recommended. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-134 APPLICATION 7540 Group 2.9 Reset 2.9 Oscillation control This paragraph explains the registers setting method and the notes relevant to the oscillation control. 2.9.1 Memory map 003816 003916 MISRG Watchdog timer control register (WDTCON) CPU mode register (CPUM) 003B16 Fig. 2.9.1 Memory map of registers relevant to oscillation control 2.9.2 Relevant registers MISRG b7 b6 b5 b4 b3 b2 b1 b0 MISRG [Address : 3816] B Name set bit after release of the STP instruction Function 0 : Set "0116" in timer 1, and "FF16" in prescaler 1 automatically 1 : Not set automatically 1 : Detection function active At reset RW 0 Oscillation stabilization time 0 1 Ceramic or RC oscillation stop 0 : Detection function inactive detection function active bit 2 These are reserved bits. Do not write "1" to these bits. 0 0 0 3 4 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 0 0 0 5 6 7 Oscillation stop detection status bit 0 : Oscillation stop not detected 1 : Oscillation stop detected (Note) Note: "0" at normal reset "1" at reset by detecting the oscillation stop Fig. 2.9.2 Structure of MISRG Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-135 APPLICATION 7540 Group 2.9 Reset Watchdog timer control register b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer control register (WDTCON) [Address : 39 16] B Name (The high-order 6 bits are read-only bits.) Function At reset RW 0 Watchdog timer H 1 2 3 4 5 6 STP instruction disable bit 7 Watchdog timer H count source selection bit 0 : STP instruction enabled 1 : STP instruction disabled 0 : Watchdog timer L underflow 1 : f(XIN)/16 1 1 1 1 1 1 0 0 Fig. 2.9.3 Structure of Watchdog timer control register CPU mode register b7 b6 b5 b4 b3 b2 b1 b0 CPU mode register (CPUM) [Address : 3B16] B Name b1 b0 Function 0 0 1 1 0 : Single-chip mode 1 : Not available 0 : Not available 1 : Not available At reset RW 0 Processor mode bits (Note 1) 1 2 Stack page selection bit 0 0 0 0 0 0 0 3 On-chip oscillator oscillation control bit 4 XIN oscillation control bit 0 : 0 page 1 : 1 page 0 : On-chip oscillator oscillation enabled 1 : On-chip oscillator oscillation stop 0 : Ceramic or RC oscillation enabled 1 : Ceramic or RC oscillation stop 0 : Ceramic oscillation 1 : RC oscillation b7 b6 5 Oscillation mode selection bit (Note 1) 6 Clock division ratio selection bits 7 0 0 : = f(XIN)/2 (high-speed mode) 0 1 : = f(XIN)/8 (middle-speed mode) 1 0 : Applied from on-chip oscillator 1 1 : = f(XIN) (double-speed mode) (Note 2) 1 Notes 1: The bit can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. However, by reset the bit is initialized and can be rewritten, again. (It is not disable to write any data to the bit for emulator MCU "M37540RSS".) 2: These bits are used only when a ceramic oscillation is selected. Do not use these when an RC oscillation is selected. Fig. 2.9.4 Structure of CPU mode register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-136 APPLICATION 7540 Group 2.9 Reset 2.9.3 Application example of on-chip oscillator The on-chip oscillator is the oscillation circuit which is equipped with the 7540 Group. External circuits can be eliminated by using this oscillator as the operation clock or by using this oscillator with a ceramic or RC oscillation circuit. When this oscillator is used as the operation clock, all peripheral functions can be used. In this section, the setting method and application example are explained. Note: The 7540 Group starts operation by the on-chip oscillator. (1) Setting method Figure 2.9.5 shows the setting method when the on-chip oscillator is used as the operation clock. Process 1: Enable on-chip oscillator oscillation. b7 b0 0 00 CPU mode register (CPUM) [Address 3B16] on-chip oscillatior oscillation enabled Process 2: Set the operation clock to on-chip oscillator. b7 b0 10 0 00 CPU mode register (CPUM) [Address 3B16] Applied from on-chip oscillator Process 3: When f(XIN) is not used, stop f(XIN). b7 b0 10 10 00 CPU mode register (CPUM) [Address 3B16] Ceramic or RC oscillation stop Fig. 2.9.5 Setting method when the on-chip oscillator is used as the operation clock (2) Example of control procedure Outline: The frequency of the on-chip oscillator is measured, and an error by the power source voltage or temperature is confirmed. Specifications: * The f(XIN) = 4 MHz is divided by timer Z and 10 ms is detected. The on-chip oscillator is divided by timer Y. * The count value of timer Y is read out in the timer Z interrupt processing routine which occurs every 10 ms, and an error from f(XIN) is confirmed. Figure 2.9.6 shows an example of control procedure. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-137 APPLICATION 7540 Group 2.9 Reset RESET Initialization SEI CLD CLT Set CPU mode register 1 0 0 0 0 0 0 CPU M(Address 3B16) Single-chip mode O n -ch ip oscilla tor oscillation enab le d f(XIN) oscillation (ceramic/RC) enabled Ceramic oscillation Applied from on-chip oscillator Wait until f(XIN) oscillation is stabilized (Note 1) Set CPU mode register 0 0 0 0 0 CPU M(Address 3B16) 00 : =f(XIN)/2 (High-speed mode) 01 : =f(XIN)/8 (Middle-speed mode) 10 : Applied from on-chip oscillator (Note 2) 11 : =f(XIN) (Double-speed mode) Set "0" to the timer Y interrupt enable bit. (Timer Y interrupt disabled) Set "0" to the timer Z interrupt enable bit. (Timer Z interrupt disabled) Set timer Y, Z mode register 1 001 0 0 TYZM(Address 2016) Timer Y: Timer mode selected Timer Y count stop Timer Z: Timer mode selected Timer Z count stop Set timer count source set register 000110 TCSS(Address 2E16) Timer Y count source: On-chip oscillator selected Timer Z: f(XIN)/2 selected Set value to prescaler Y, timer Y "FF16" "FF16" Prescaler Y (Address 2116) Timer Y (Address 2316) Set value to prescaler Z, timer Z (Note 3) "F916" "4F16" Prescaler Z (Address 2516) Timer Z primary (Address 2716) Set "0" to the timer Y interrupt request bit. Set "0" to the timer Z interrupt request bit. Set "1" to the timer Z interrupt enable bit. (Timer Z interrupt enabled) Set timer Y, Z mode register 0 000 0 0 TYZM(Address 2016) Notes 1: For the concrete time, ask the oscillator manufacture. 2: In this example, this setting cannot be selected. 3: 10 ms = 1/4 MHz 2 (F916 + 1) (4F16 + 1) Timer Z division ratio Prescaler Z Timer Z primary Timer Y count start Timer Z count start CLI Timer Z interrupt processing routine Read prescaler Y and timer Y and compare their complement with the setting values of prescaler Z and timer Z Processing Processing RTI Fig. 2.9.6 Control procedure Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-138 APPLICATION 7540 Group 2.9 Reset 2.9.4 Oscillation stop detection circuit The oscillation stop detection circuit can be used to detect the stop by some failure or disconnection of an external ceramic oscillation circuit. In this section, the setting method and application example. (1) Operation description When the stop of an external oscillation circuit is detected by the oscillation stop detection circuit, the oscillation stop detection status bit of MISRG is set to "1" and the internal reset occurs. The 7540 Group starts operation by the on-chip oscillator after system is released from reset. Accordingly, error of the external oscillation circuit can be detected by checking the oscillation stop detection status bit after system starts operation. Notes 1: When the stop mode is used, set the oscillation stop detection function to "invalid". 2: When f(XIN) oscillation is stopped, set the oscillation stop detection function to "invalid". Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-139 APPLICATION 7540 Group 2.9 Reset (2) Setting method Figure 2.9.7 shows the initial setting method oscillation stop detection circuit. Figure 2.9.8 shows the setting method for the oscillation stop detection circuit in the main processing. * Execute the following set at the beginning of program after system is released from reset. Process 1: Check that reset by oscillation stop detection is executed by referring the oscillation stop detection status bit. b7 b0 00000 MISRG (MISRG) [Address 3816] Oscillation stop detection status bit 0: Oscillation stop not detected 1: Oscillation stop detected * Oscillation stop is detected Some error occus in the oscillation circuit. Do not switch the operation clock and execute the processing when some error occurs. * Oscillation stop is not detected Execute the Process 2. Process 2: Select oscillation mode. b7 b0 10 00 00 CPU mode register (CPUM) [Address 3B16] Oscillation mode selection bit (Note) 0: Ceramic oscillation 1: RC oscillation Note: The bit can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. However, by reset the bit is initialized and can be rewritten, again. (It is not disable to write any data to the bit for emulator MCU "M37540RSS"). Process 3: Wait oscillation stabilizing (Note). Note: This process can be eliminated when the RC oscillation is selected. For the oscillation stabilizing time, ask the oscillator manufacture. Process 4: Set the ceramic or RC oscillation stop detection function active bit. b7 b0 000001 MISRG (MISRG) [Address 3816] Detection function active (Note) Note: When some error occurs in the oscillation circuit, system is released from reset after setting of Process 4 is executed. Process 5: Select clock division ratio. b7 b0 00 CPU mode register (CPUM) [Address 3B16] Clock division ratio selection bits b7b6 0 0: f() = f(XIN)/2 (high-speed mode) 0 1: f()= f(XIN)/8 (middle-speed mode) 1 0: Applied from on-chip oscillator 1 1: f()=f(XIN) (double-speed mode) (Note) Note: These bits are used only when a ceramic oscillation is selected. Do not use these when an RC oscillation is selected. Fig. 2.9.7 Initial setting method for the oscillation stop detection circuit Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-140 APPLICATION 7540 Group 2.9 Reset Process: Start on-chip oscillation when it is stopped. b7 b0 00 00 CPU mode register (CPUM) [Address 3B16] On-chip oscillatior oscillation enabled Process 2: Set ceramic or RC oscillation stop detection function active bit. b7 b0 000001 MISRG (MISRG) [Address 3816] Detection function active (Note) Note: When some error occurs in the oscillation circuit, system is released from reset after setting of Process 2 is executed. Fig. 2.9.8 Setting method for the oscillation stop detection circuit in main processing Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-141 APPLICATION 7540 Group 2.9 Reset 2.9.5 State transition In the 7540 Group, the operation clock is selected from the following 4 types. * f(XIN)/2 (high-speed mode) * f(XIN)/8 (middle-speed mode) * On-chip oscillator * f(XIN) (double-speed mode) (Note 1) Note 1: f(XIN) can be used only at the ceramic oscillation. Do not use f(XIN) at RC oscillation. Also, in the 7540 Group, the function to stop CPU operation by software and to keep CPU wait in the following 2-type low power dissipation. q Stop mode with the STP instruction (Notes 2, 3, 4, 5, 6, 7) q Wait mode with the WIT instruction (Note 8) Notes 2: When the stop mode is used, set the oscillation stop detection function to "invalid". 3: When the stop mode is used, set "0" (STP instruction enabled) the STP instruction disable bit of the watchdog timer control register. 4: Timer 1 can be used to set the oscillation stabilizing time after release of the STP instruction. The oscillation stabilizing time after release of STP instruction can be selected from "set automatically"/ "not set automaticallzy" by the oscillation stabilizing time set bit after release of the STP instruction of MISRG. When "0" is set to this bit, "0116" is set to timer 1 and "FF16" is set to prescaler 1 automatically. When "1" is set to this bit, nothing is set to timer 1 and prescaler 1. Therefore, set the wait time according to the oscillation stabilizing time of the oscillation. Also, when timer 1 is used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode. 5: The STP instruction cannot be used during CPU is operating by the on-chip oscillator. 6: When the stop mode is used, stop the on-chip oscillator oscillation. 7: Do not execute the STP instruction during the A/D conversion. 8: When the wait mode is used, stop the clock except the operation clock source. Figure 2.9.9 shows the state transition. Stop mode Interrupt Interrupt STP instruction Wait mode WIT instruction Interrupt WIT instruction State 3 Operation clock source: On-chip oscillator (Note 3) f(XIN) oscillation enabled On-chip oscillator enalbed CPUM412 State 1 Operation clock source: f(XIN) (Note 1) f(XIN) oscillation enabled On-chip oscillator stop CPUM302 CPUM312 State 2 CPUM76102 Operation clock source: f(XIN) (Note 1) f(XIN) oscillation enabled On-chip oscillator enabled CPUM76002 012 112 (Note 2) CPUM402 State 4 Operation clock source: On-chip oscillator (Note 3) f(XIN) oscillation stop On-chip oscillator enalbed MISRG112 MISRG102 MISRG112 MISRG102 State 2' CPUM76102 Operation clock source: f(XIN) (Note 1) f(XIN) oscillation enabled On-chip oscillator enabled CPUM76002 012 112 (Note 2) State 3' Operation clock source: On-chip oscillator (Note 3) f(XIN) oscillation enabled On-chip oscillator enalbed Oscillation stop detection circuit valid Reset released Reset state Notes on switch of clock (1) In operation clock source = f(XIN), the following can be selected for the CPU clock division ratio. q f(XIN)/2 (high-speed mode) q f(XIN)/8 (middle-speed mode) q f(XIN) (double-speed mode, only at a ceramic oscillation) (2) Execute the state transition state 3 to state 2 or state 3' to state 2' after stabilizing XIN oscillation. (3) In operation clock source = on-chip oscillator, the middlespeed mode is selected for the CPU clock division ratio. (4) When the state transition state 2 state 3 state 4 is performed, execute the NOP instruction as shown below according to the division ratio of CPU clock. * CPUM76 102 (State 2 state 3) * NOP instruction * CPUM4 12 (State 3 state 4) Double-speed mode at on-chip oscillator: NOP 3 High-speed mode at on-chip oscillator: NOP 1 Middle-speed mode at on-chip oscillator: NOP 0 Fig. 2.9.9 State transition Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-142 APPLICATION 7540 Group 2.9 Reset (1) Example of control procedure Outline: The on-chip oscillator is used, and the intermittent operation for the low-power dissipation can be realized. Specifications: A mode is selected from the following modes 1 to 4 according to the usage condition. The return from mode 1 is executed by the timer A interrupt request which occurs every 0.5 s. Mode 1: Wait mode by the on-chip oscillator oscillation Operation clock source: On-chip oscillator CPU stop, ceramic oscillation stop, on-chip oscillator oscillation Mode 2: Middle-speed mode by the on-chip oscillator oscillation Operation clock source: On-chip oscillator CPU operation, ceramic oscillation stop, on-chip oscillator oscillation Mode 3: Middle-speed mode by the ceramic oscillation Operation clock source: Ceramic oscillation CPU operation, ceramic oscillation, on-chip oscillator oscillation Mode 4: Double-speed mode by the ceramic oscillation Operation clock source: Ceramic oscillation CPU operation, ceramic oscillation, on-chip oscillator oscillation Figure 2.9.10 shows an example of mode transition and Figure 2.9.11 shows an example of control procedure. Mode 4 Ceramic oscillation Double-speed mode (1/1) Power dissipation Ceramic oscillation start Middle-speed mode (1/8) CPU operation is started by interrupt of timer underflow Mode 3 Wait m ode by on-chip oscillation * CPU stop * TImer operating Mode 1 Mode 2 Mode 1 Mode 2 Mode 1 Mode 2 Mode 1 Mode 2 Time Fig. 2.9.10 Example of mode transition Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-143 APPLICATION 7540 Group 2.9 Reset RESET Initialization SEI CLD CLT Operation mode by ceramic oscillation Mode 3 Set CPU mode register 10010 00 CPUM(Address 3B16) Single-chip mode O n -ch ip oscilla tor oscillation enab le d f(XIN) oscillation (ceramic) stop Ceramic oscillation Ap plied from on-chip oscillator (N o te 1) Set CPU mode register 1000 0 0 0 CPUM(Address 3B16) f(XIN) oscillation (ceramic) enabled Wait until f(XIN) oscillation is stabilized (Note 4) Set CPU mode register Mode 2 Set "0" to the timer A interrupt enable bit. (Timer A interrupt disabled) Set timer A mode register 1 00 0100 0 00 CPUM(Address 3B16) Middle-speed mode Processing TAM(Address 1D16) Timer mode selected Count stop Switch to double-speed mode is required? N Y Mode 4 Set values to timer A (Notes 2, 3) "2316" "F416" T im er A (low -order) [A ddress 1 E1 6] T im er A (high-o rder) [A ddress 1F1 6] Set CPU mode register 1100 0 0 0 CPUM(Address 3B16) Double-speed mode Set "0" to the timer A interrupt request bit Set "0" to the timer A interrupt enable bit. (Timer A interrupt disabled) Set "0" to other interrupt enable bits. (Other interrups disabled) CLI Set timer A mode register TAM(Address 1D16) 0 00 Count start WIT instruction executed Processing Modes 3, 4 (common) Set CPU mode register 10010 0 0 CPUM(Address 3B16) O n -ch ip oscilla tor oscillation enab le d XIN oscillation (ceramic) stop Applied from on-chip oscillator RTS Mode 1 Wait mode Mode 2 Timer A interrupt processing routine Processing RTI Mode 2 Set timer A mode register 1 00 TAM(Address 1D16) Count stop Processing Notes 1: At VCC = 5 V, the timer A count source when an on-chip oscillator is selected as the operation clock is as follows; About 2 MHz / 16 = about 125 kHz Timer A division ratio (fixed) Switch to ceramic oscillation is required? N 2: When setting the value to timer, set in order of low-order byte and high-order byte following. 3: 0.5 s = 1/125 kHz (F42316 + 1) Timer A setting value Y Modes 3, 4 Operation mode by ceramic oscillation 4: For the concrete time, ask the oscillator manufacture. Fig. 2.9.11 Control procedure Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-144 APPLICATION 7540 Group 2.9 Reset 2.9.6 Notes on oscillation stop detection circuit Notes on using oscillation stop detection circuit are described below. (1) Note on on-chip oscillator The 7540 Group starts operation by the on-chip oscillator. On-chip oscillator operation The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. (2) Notes on oscillation circuit stop detection circuit When the stop mode is used, set the oscillation stop detection function to "invalid". When f(XIN) oscillation is stopped, set the oscillation stop detection function to "invalid". The oscillation stop detection circuit is not included in the emulator MCU "M37540RSS". (3) Notes on stop mode When the stop mode is used, set the oscillation stop detection function to "invalid". When the stop mode is used, set "0" (STP instruction enabled) to the STP instruction disable bit of the watchdog timer control register. Timer 1 can be used to set the oscillation stabilizing time after release of the STP instruction. The oscillation stabilizing time after release of STP instruction can be selected from "set automatically"/ "not set automatically" by the oscillation stabilizing time set bit after release of the STP instruction of MISRG. When "0" is set to this bit, "0116" is set to timer 1 and "FF16" is set to prescaler 1 automatically. When "1" is set to this bit, nothing is set to timer 1 and prescaler 1. Therefore, set the wait time according to the oscillation stabilizing time of the oscillation. Also, when timer 1 is used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode. The STP instruction cannot be used during CPU is operating by the on-chip oscillator. When the stop mode is used, stop the on-chip oscillator oscillation. Do not execute the STP instruction during the A/D conversion. (4) Note on wait mode When the wait mode is used, stop the clock except the operation clock source. (5) Notes on state transition When the operation clock source is f(XIN), the CPU clock division ratio can be selected from the following; * f(XIN)/2 (high-speed mode) * f(XIN)/8 (middle-speed mode) * f(XIN) (double-speed mode) The double-speed mode can be used only at ceramic oscillation. Do not use the mode at RC oscillation. Stabilize the f(XIN) oscillation to change the operation clock source from the on-chip oscillator to f(XIN). Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-145 APPLICATION 7540 Group 2.9 Reset When the on-chip oscillation is used as the operation clock, the CPU clock division ratio is the middle-speed mode. When the state transition state 2state 3state 4 is performed, execute the NOP instruction as shown below according to the division ratio of CPU clock. * CPUM76102 (State 2state 3) * NOP instruction * CPUM412 (State 3state 4) Double-speed mode at on-chip oscillator: NOP3 High-speed mode at on-chip oscillator: NOP1 Middle-speed mode at on-chip oscillator: NOP0 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 2-146 CHAPTER 3 APPENDIX 3.1 3.2 3.3 3.4 Electrical characteristics Typical characteristics Notes on use Countermeasures against noise 3.5 List of registers 3.6 Package outline 3.7 List of instruction code 3.8 Machine instructions 3.9 SFR memory map 3.10 Pin configurations 3.11 Differences between 7540 Group and 7531 Group APPENDIX 7540 Group 3.1 Electrical characteristics 3.1 Electrical characteristics 3.1.1 7540 Group (General purpose) Applied to: M37540M2-XXXFP/SP/GP, M37540M4-XXXFP/SP/GP, M37540E2FP/SP/GP, M37540E8FP/SP/GP (1) Absolute Maximum Ratings (General purpose) Table 3.1.1 Symbol VCC VI VI VI VO Pd Topr Tstg Absolute maximum ratings Parameter Power source voltage Input voltage P00-P07, P10-P14, P20-P27, P30-P37, VREF Input voltage RESET, XIN Input voltage CNVSS (Note 2) Output voltage P00-P07, P10-P14, P20-P27, P30-P37, XOUT Power dissipation Operating temperature Storage temperature Conditions Ratings -0.3 to 6.5 (Note 1) -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -0.3 to 13 -0.3 to VCC + 0.3 300 (Note 3) -20 to 85 -40 to 125 Unit V V V V V mW C C All voltages are based on VSS. Output transistors are cut off. Ta = 25C Notes 1: This is the rating value for the Mask ROM version. The rating value for the One Time PROM version is -0.3 to 7.0 V. 2: It is a rating only for the One Time PROM version. Connect to VSS for the mask ROM version. 3: 200 mW for the 32P6U package product. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-2 APPENDIX 7540 Group 3.1 Electrical characteristics (2) Recommended Operating Conditions (General purpose) Table 3.1.2 Symbol VCC Power source voltage (ceramic) Recommended operating conditions (1) (VCC = 2.2 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) Parameter f(XIN) = 8 MHz (High-, Middle-speed mode) f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 2 MHz (High-, Middle-speed mode) f(XIN) = 6 MHz (Double-speed mode) f(XIN) = 4 MHz (Double-speed mode) f(XIN) = 2 MHz (Double-speed mode) f(XIN) = 1 MHz (Double-speed mode) f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 2 MHz (High-, Middle-speed mode) f(XIN) = 1 MHz (High-, Middle-speed mode) Limits Min. 4.0 2.4 2.2 4.5 4.0 2.4 2.2 4.0 2.4 2.2 2.0 0.8VCC 2.0 0.8VCC 0 0 0 0 Typ. 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 VCC VCC VCC VCC 0.3VCC 0.8 0.2VCC 0.16VCC -80 80 60 -40 40 30 Unit V V V V V V V V V V V V V V V V V V V mA mA mA mA mA mA Power source voltage (RC) VSS VREF VIH VIH VIH VIL VIL VIL VIL IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) Power source voltage Analog reference voltage "H" input voltage P00-P07, P10-P14, P20-P27, P30-P37 "H" input voltage (TTL input level selected) P10, P12, P13, P36, P37 (Note 1) "H" input voltage RESET, XIN "L" input voltage P00-P07, P10-P14, P20-P27, P30-P37 "L" input voltage (TTL input level selected) P10, P12, P13, P36, P37 (Note 1) "L" input voltage RESET, CNVSS "L" input voltage XIN "H" total peak output current (Note 2) P00-P07, P10-P14, P20-P27, P30-P37 "L" total peak output current (Note 2) P00-P07, P10-P14, P20-P27, P37 "L" total peak output current (Note 2) P30-P36 "H" total average output current (Note 2) P00-P07, P10-P14, P20-P27, P30-P37 "L" total average output current (Note 2) P00-P07, P10-P14, P20-P27, P37 "L" total average output current (Note 2) P30-P36 Note 1: Vcc = 4.0 to 5.5V 2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-3 APPENDIX 7540 Group 3.1 Electrical characteristics Table 3.1.3 Recommended operating conditions (2) (VCC = 2.2 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) Parameter "H" peak output current (Note 1) P00-P07, P10-P14, P20-P27, P30-P37 "L" peak output current (Note 1) P00-P07, P10-P14, P20-P27, P37 "L" peak output current (Note 1) P30-P36 "H" average output current (Note 2) P00-P07, P10-P14, P20-P27, P30-P37 "L" average output current (Note 2) P00-P07, P10-P14, P20-P27, P37 "L" average output current (Note 2) P30-P36 Internal clock oscillation frequency (Note 3) VCC = 4.5 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) VCC = 2.2 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V at ceramic oscillation or external clock input High-, Middle-speed mode Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V at ceramic oscillation or external clock input High-, Middle-speed mode Internal clock oscillation frequency (Note 3) VCC = 2.2 to 5.5 V at ceramic oscillation or external clock input High-, Middle-speed mode Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V at RC oscillation High-, Middle-speed mode Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V at RC oscillation High-, Middle-speed mode Internal clock oscillation frequency (Note 3) VCC = 2.2 to 5.5 V at RC oscillation High-, Middle-speed mode Limits Min. Typ. Max. -10 10 30 -5 5 15 6 4 2 1 8 4 2 4 2 1 Unit mA mA mA mA mA mA MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Symbol IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN) Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50 %. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-4 APPENDIX 7540 Group 3.1 Electrical characteristics (3) Electrical Characteristics (General purpose) Table 3.1.4 Electrical characteristics (1) VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Limits Symbol VOH Parameter "H" output voltage P00-P07, P10-P14, P20-P27, P30-P37 (Note 1) Test conditions IOH = -5 mA VCC = 4.0 to 5.5 V IOH = -1.0 mA VCC = 2.2 to 5.5 V IOL = 5 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 2.2 to 5.5 V IOL = 15 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 10 mA VCC = 2.2 to 5.5 V Min. VCC-1.5 VCC-1.0 1.5 0.3 1.0 2.0 0.3 1.0 0.4 Typ. Max. Unit V V V V V V V V V VOL "L" output voltage P00-P07, P10-P14, P20-P27, P37 VOL "L" output voltage P30-P36 VT+-VT- VT+-VT- VT+-VT- IIH Hysteresis CNTR0, CNTR1, INT0, INT1(Note 2) P00-P07 (Note 3) Hysteresis RXD, SCLK1, SCLK2, SDATA2 (Note 2) Hysteresis RESET "H" input current P00-P07, P10-P14, P20-P27, P30-P37 "H" input current RESET "H" input current XIN "L" input current P00-P07, P10-P14, P20-P27, P30-P37 "L" input current RESET, CNVSS "L" input current XIN "L" input current P00-P07, P30-P37 RAM hold voltage On-chip oscillator oscillation frequency Oscillation stop detection circuit detection frequency 0.5 0.5 VI = VCC (Pin floating. Pull up transistors "off") VI = VCC VI = VCC VI = VSS (Pin floating. Pull up transistors "off") VI = VSS VI = VSS VI = VSS (Pull up transistors "on") When clock stopped VCC = 5.0 V, Ta = 25 C VCC = 5.0 V, Ta = 25 C -4.0 -0.2 2.0 1000 62.5 -0.5 5.5 3000 187.5 4.0 -5.0 5.0 V V A A A A A A mA V kHz kHz IIH IIH IIL 5.0 IIL IIL IIL VRAM ROSC DOSC -5.0 2000 125 Notes 1: P11 is measured when the P11/TXD1 P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: RXD1, SCLK1, SCLK2, SDATA2, INT0, and INT1 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to "0" (CMOS level). 3: It is available only when operating key-on wake up. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-5 APPENDIX 7540 Group 3.1 Electrical characteristics Table 3.1.5 Electrical characteristics (2) (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Limits Test conditions One Time PROM version High-speed mode, f(XIN) = 8 MHz Output transistors "off" High-speed mode, f(XIN) = 2 MHz, VCC = 2.2 V Output transistors "off" Double-speed mode, f(XIN) = 6 MHz Output transistors "off" Middle-speed mode, f(XIN) = 8 MHz Output transistors "off" On-chip oscillator operation mode, VCC = 5 V Output transistors "off" f(XIN) = 8 MHz (in WIT state), functions except timer 1 disabled, Output transistors "off" f(XIN) = 2 MHz, VCC = 2.2 V (in WIT state), functions except timer 1 disabled, Output transistors "off" On-chip oscillator operation mode, VCC = 5V Output transistors "off" Increment when A/D conversion is executed f(XIN) = 8 MHz, VCC = 5 V All oscillation stopped Ta = 25 C (in STP state) Ta = 85 C Output transistors "off" High-speed mode, f(XIN) = 8 MHz Output transistors "off" High-speed mode, f(XIN) = 2 MHz, VCC = 2.2 V Output transistors "off" Double-speed mode, f(XIN) = 6 MHz Output transistors "off" Middle-speed mode, f(XIN) = 8 MHz Output transistors "off" On-chip oscillator operation mode, VCC = 5 V Output transistors "off" f(XIN) = 8 MHz (in WIT state), functions except timer 1 disabled, Output transistors "off" f(XIN) = 2 MHz, VCC = 2.2 V (in WIT state), functions except timer 1 disabled, Output transistors "off" On-chip oscillator operation mode, VCC = 5V Output transistors "off" Increment when A/D conversion is executed f(XIN) = 8 MHz, VCC = 5 V Ta = 25 C All oscillation stopped (in STP state) Ta = 85 C Output transistors "off" Min. Typ. 5.0 0.5 6.0 2.0 350 1.6 Max. 8.0 1.5 10.0 5.0 1000 3.2 Unit mA mA mA mA A mA Symbol ICC Parameter Power source current 0.2 mA 150 0.5 0.1 450 A mA 1.0 10 6.5 1.2 8.0 5.0 900 3.2 A A mA mA mA mA A mA Mask ROM version 3.5 0.4 4.5 2.0 300 1.6 0.2 mA 150 0.5 0.1 450 A mA 1.0 10 A A Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-6 APPENDIX 7540 Group 3.1 Electrical characteristics (4) A/D Converter Characteristics (General purpose) Table 3.1.6 A/D Converter characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol -- -- -- VOT One Time PROM version VFST Resolution Linearity error Differential nonlinear error Zero transition voltage Full scale transition voltage Parameter Test conditions Limits Min. Typ. Max. 10 3 0.9 0 0 5105 3060 5 3 5115 3069 55 150 70 20 15 5125 3075 122 200 120 5.0 10 3 1.5 0 0 5105 3060 15 9 5125 3075 55 150 70 35 21 5150 3090 122 200 120 5.0 Unit Bits LSB LSB mV mV mV mV tc(XIN) k A A Bits LSB LSB mV mV mV mV tc(XIN) k A A VCC = 2.7 to 5.5 V Ta = 25 C VCC = 2.7 to 5.5 V Ta = 25 C VCC = VREF = 5.12 V VCC = VREF = 3.072 V VCC = VREF = 5.12 V VCC = VREF = 3.072 V tCONV Conversion time RLADDER Ladder resistor IVREF Reference power source input current II(AD) -- -- -- VOT Mask ROM version VFST A/D port input current Resolution Linearity error Differential nonlinear error Zero transition voltage Full scale transition voltage VREF = 5.0 V VREF = 3.0 V 50 50 VCC = 2.7 to 5.5 V Ta = 25 C VCC = 2.7 to 5.5 V Ta = 25 C VCC = VREF = 5.12 V VCC = VREF = 3.072 V VCC = VREF = 5.12 V VCC = VREF = 3.072 V tCONV Conversion time RLADDER Ladder resistor IVREF Reference power source input current II(AD) A/D port input current VREF = 5.0 V VREF = 3.0 V 50 50 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-7 APPENDIX 7540 Group 3.1 Electrical characteristics (5) Timing Requirements (General purpose) Table 3.1.7 Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(CNTR1) tWH(CNTR1) tWL(CNTR1) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD1-SCLK1) th(SCLK1-RxD1) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SDATA2-SCLK2) th(SCLK2-SDATA2) Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0 input cycle time CNTR0, INT0, INT1, input "H" pulse width CNTR0, INT0, INT1, input "L" pulse width CNTR1 input cycle time CNTR1 input "H" pulse width CNTR1 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input "H" pulse width (Note) Serial I/O1 clock input "L" pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 input set up time Serial I/O2 input hold time Min. 2 125 50 50 200 80 80 2000 800 800 800 370 370 220 100 1000 400 400 200 200 Limits Typ. Max. s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to "1" (clock synchronous serial I/O1 is selected). When bit 6 of the serial I/O1 control register is "0" (clock asynchronous serial I/O1 is selected), the rating values are divided by 4. Table 3.1.8 Symbol Timing requirements (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0 input cycle time CNTR0, INT0, INT1, input "H" pulse width CNTR0, INT0, INT1, input "L" pulse width CNTR1 input cycle time CNTR1 input "H" pulse width CNTR1 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input "H" pulse width (Note) Serial I/O1 clock input "L" pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 input set up time Serial I/O2 input hold time Min. 2 250 100 100 500 230 230 4000 1600 1600 2000 950 950 400 200 2000 950 950 400 400 Limits Typ. Max. s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(CNTR1) tWH(CNTR1) tWL(CNTR1) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD1-SCLK1) th(SCLK1-RxD1) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SDATA2-SCLK2) th(SCLK2-SDATA2) Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to "1" (clock synchronous serial I/O1 is selected). When bit 6 of the serial I/O1 control register is "0" (clock asynchronous serial I/O1 is selected), the rating values are divided by 4. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-8 APPENDIX 7540 Group 3.1 Electrical characteristics Table 3.1.9 Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(CNTR1) tWH(CNTR1) tWL(CNTR1) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD1-SCLK1) Timing requirements (3) (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0 input cycle time CNTR0, INT0, INT1, input "H" pulse width CNTR0, INT0, INT1, input "L" pulse width CNTR1 input cycle time CNTR1 input "H" pulse width CNTR1 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input "H" pulse width (Note) Serial I/O1 clock input "L" pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 input set up time Serial I/O2 input hold time Min. 2 500 200 200 1000 460 460 8000 3200 3200 4000 1900 1900 800 400 4000 1900 1900 800 800 Limits Typ. Max. s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit th(SCLK1-RxD1) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SDATA2-SCLK2) th(SCLK2-SDATA2) Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to "1" (clock synchronous serial I/O1 is selected). When bit 6 of the serial I/O1 control register is "0" (clock asynchronous serial I/O1 is selected), the rating values are divided by 4. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-9 APPENDIX 7540 Group 3.1 Electrical characteristics (6) Switching Characteristics (General purpose) Table 3.1.10 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1-TxD1) tv(SCLK1-TxD1) tr(SCLK1) tf(SCLK1) tWH(SCLK2) tWL(SCLK2) td(SCLK2-SDATA2) tv(SCLK2-SDATA2) tr(SCLK2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) Limits Min. tC(SCLK1)/2-30 tC(SCLK1)/2-30 140 -30 30 30 tC(SCLK2)/2-30 tC(SCLK2)/2-30 140 0 30 30 30 30 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 Note 1: Pin XOUT is excluded. Table 3.1.11 Switching characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1-TxD1) tv(SCLK1-TxD1) tr(SCLK1) tf(SCLK1) tWH(SCLK2) tWL(SCLK2) td(SCLK2-SDATA2) tv(SCLK2-SDATA2) tr(SCLK2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) Limits Min. tC(SCLK1)/2-50 tC(SCLK1)/2-50 350 -30 50 50 tC(SCLK2)/2-50 tC(SCLK2)/2-50 350 0 50 50 50 50 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 20 20 Note 1: Pin XOUT is excluded. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-10 APPENDIX 7540 Group 3.1 Electrical characteristics Table 3.1.12 Switching characteristics (3) (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1-TxD1) tv(SCLK1-TxD1) tr(SCLK1) tf(SCLK1) tWH(SCLK2) tWL(SCLK2) td(SCLK2-SDATA2) tv(SCLK2-SDATA2) tr(SCLK2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) Limits Min. tC(SCLK1)/2-70 tC(SCLK1)/2-70 450 -30 70 70 tC(SCLK2)/2-70 tC(SCLK2)/2-70 450 0 70 70 70 70 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 25 25 Note 1: Pin XOUT is excluded. Measured output pin 100 pF /// CMOS output Fig. 3.1.1 Switching characteristics measurement circuit diagram (General purpose) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-11 APPENDIX 7540 Group 3.1 Electrical characteristics tC(CNTR0) tWH(CNTR0) tWL(CNTR0) 0.2VCC CNTR0 0.8VCC tC(CNTR1) tWH(CNTR1) tWL(CNTR1) 0.2VCC CNTR1 0.8VCC tWH(CNTR0) tWL(CNTR0) 0.2VCC INT0, INT1 0.8VCC tW(RESET) RESET 0.2VCC 0.8VCC tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC XIN 0.8VCC tf tWL(SCLK1) 0.2VCC tC(SCLK1) tr 0.8VCC tWH(SCLK1) SCLK1 tsu(RxD1-SCLK1) th(SCLK1-RxD1) RXD1 (at receive) td(SCLK1-TxD1) 0.8VCC 0.2VCC tv(SCLK1-TxD1) TXD1 (at transmit) tf tWL(SCLK2) 0.2VCC tC(SCLK2) tr 0.8VCC tWH(SCLK2) SCLK2 tsu(SDATA2-SCLK2) th(SCLK2-SDATA2) SDATA2 (at receive) td(SCLK2-SDATA2) 0.8VCC 0.2VCC tv(SCLK2-SDATA2) SDATA2 (at transmit) Fig. 3.1.2 Timing chart (General purpose) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-12 APPENDIX 7540 Group 3.1 Electrical characteristics 3.1.2 7540Group (Extended operating temperature version) Applied to: M37540M2T-XXXFP/GP, M37540M4T-XXXFP/GP, M37540E8T-XXXFP/GP (2) Absolute Maximum Ratings (Extended operating temperature version) Table 3.1.13 Absolute maximum ratings Symbol VCC VI VI VO Pd Topr Tstg Parameter Power source voltage Input voltage P00-P07, P10-P14, P20-P27, P30-P37, VREF Input voltage RESET, XIN, CNVSS Output voltage P00-P07, P10-P14, P20-P27, P30-P37, XOUT Power dissipation Operating temperature Storage temperature Conditions Ratings -0.3 to 6.5 (Note 1) -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 300 (Note 2) -40 to 85 -65 to 150 Unit V V V V mW C C All voltages are based on VSS. Output transistors are cut off. Ta = 25C Notes 1: This is the rating value for the Mask ROM version. The rating value for the One Time PROM version is -0.3 to 7.0 V. 2: 200 mW for the 32P6U package product. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-13 APPENDIX 7540 Group 3.1 Electrical characteristics (2) Recommended Operating Conditions (Extended operating temperature version) Table 3.1.14 Recommended operating conditions (1) (VCC = 2.4 to 5.5 V, Ta = -40 to 85 C, unless otherwise noted) Symbol VCC Power source voltage (ceramic) Parameter f(XIN) = 8 MHz (High-, Middle-speed mode) f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 6 MHz (Double-speed mode) f(XIN) = 4 MHz (Double-speed mode) f(XIN) = 2 MHz (Double-speed mode) f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 2 MHz (High-, Middle-speed mode) Limits Min. 4.0 2.4 4.5 4.0 2.4 4.0 2.4 2.0 0.8VCC 2.0 0.8VCC 0 0 0 0 Typ. 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 VCC VCC VCC VCC 0.3VCC 0.8 0.2VCC 0.16VCC -80 80 60 -40 40 30 Unit V V V V V V V V V V V V V V V V mA mA mA mA mA mA Power source voltage (RC) VSS VREF VIH VIH VIH VIL VIL VIL VIL IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) Power source voltage Analog reference voltage "H" input voltage P00-P07, P10-P14, P20-P27, P30-P37 "H" input voltage (TTL input level selected) P10, P12, P13, P36, P37 (Note 1) "H" input voltage RESET, XIN "L" input voltage P00-P07, P10-P14, P20-P27, P30-P37 "L" input voltage (TTL input level selected) P10, P12, P13, P36, P37 (Note 1) "L" input voltage RESET, CNVSS "L" input voltage XIN "H" total peak output current (Note 2) P00-P07, P10-P14, P20-P27, P30-P37 "L" total peak output current (Note 2) P00-P07, P10-P14, P20-P27, P37 "L" total peak output current (Note 2) P30-P36 "H" total average output current (Note 2) P00-P07, P10-P14, P20-P27, P30-P37 "L" total average output current (Note 2) P00-P07, P10-P14, P20-P27, P37 "L" total average output current (Note 2) P30-P36 Note 1: Vcc = 4.0 to 5.5V 2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-14 APPENDIX 7540 Group 3.1 Electrical characteristics Table 3.1.15 Recommended operating conditions (2) (VCC = 2.4 to 5.5 V, Ta = -40 to 85 C, unless otherwise noted) Symbol IOH(peak) Parameter Limits Min. Typ. Max. -10 10 30 -5 5 15 6 4 2 8 4 4 2 Unit mA mA mA mA mA mA MHz MHz MHz MHz MHz MHz MHz "H" peak output current (Note 1) P00-P07, P10-P14, P20-P27, P30-P37 "L" peak output current (Note 1) P00-P07, P10-P14, P20-P27, P37 IOL(peak) "L" peak output current (Note 1) P30-P36 IOL(peak) "H" average output current (Note 2) P00-P07, P10-P14, P20-P27, P30-P37 IOH(avg) "L" average output current (Note 2) P00-P07, P10-P14, P20-P27, P37 IOL(avg) "L" average output current (Note 2) P30-P36 IOL(avg) Internal clock oscillation frequency (Note 3) VCC = 4.5 to 5.5 V f(XIN) at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V at ceramic oscillation or external clock input High-, Middle-speed mode Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V at ceramic oscillation or external clock input High-, Middle-speed mode Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V at RC oscillation High-, Middle-speed mode Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V at RC oscillation High-, Middle-speed mode Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50 %. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-15 APPENDIX 7540 Group 3.1 Electrical characteristics (3) Electrical Characteristics (Extended operating temperature version) Table 3.1.16 Electrical characteristics (1) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Limits Symbol VOH Parameter "H" output voltage P00-P07, P10-P14, P20-P27, P30-P37 (Note 1) Test conditions IOH = -5 mA VCC = 4.0 to 5.5 V IOH = -1.0 mA VCC = 2.4 to 5.5 V IOL = 5 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 2.4 to 5.5 V IOL = 15 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 10 mA VCC = 2.4 to 5.5 V Min. VCC-1.5 VCC-1.0 1.5 0.3 1.0 2.0 0.3 1.0 0.4 Typ. Max. Unit V V V V V V V V V VOL "L" output voltage P00-P07, P10-P14, P20-P27, P37 VOL "L" output voltage P30-P36 VT+-VT- VT+-VT- VT+-VT- IIH Hysteresis CNTR0, CNTR1, INT0, INT1(Note 2) P00-P07 (Note 3) Hysteresis RXD, SCLK1, SCLK2, SDATA2 (Note 2) Hysteresis RESET "H" input current P00-P07, P10-P14, P20-P27, P30-P37 "H" input current RESET "H" input current XIN "L" input current P00-P07, P10-P14, P20-P27, P30-P37 "L" input current RESET, CNVSS "L" input current XIN "L" input current P00-P07, P30-P37 RAM hold voltage On-chip oscillator oscillation frequency Oscillation stop detection circuit detection frequency 0.5 0.5 VI = VCC (Pin floating. Pull up transistors "off") VI = VCC VI = VCC VI = VSS (Pin floating. Pull up transistors "off") VI = VSS VI = VSS VI = VSS (Pull up transistors "on") When clock stopped VCC = 5.0 V, Ta = 25 C VCC = 5.0 V, Ta = 25 C -4.0 -0.2 2.0 1000 62.5 -0.5 5.5 3000 187.5 4.0 -5.0 5.0 V V A A A A A A mA V kHz kHz IIH IIH IIL 5.0 IIL IIL IIL VRAM ROSC DOSC -5.0 2000 125 Notes 1: P11 is measured when the P11/TXD1 P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: RXD1, SCLK1, SCLK2, SDATA2, INT0, and INT1 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to "0" (CMOS level). 3: It is available only when operating key-on wake up. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-16 APPENDIX 7540 Group 3.1 Electrical characteristics Table 3.1.17 Electrical characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Limits Symbol ICC Test conditions One Time PROM version High-speed mode, f(XIN) = 8 MHz Output transistors "off" High-speed mode, f(XIN) = 2 MHz, VCC = 2.4 V Output transistors "off" Double-speed mode, f(XIN) = 6 MHz, Output transistors "off" Middle-speed mode, f(XIN) = 8 MHz, Output transistors "off" On-chip oscillator operation mode, VCC = 5 V Output transistors "off" f(XIN) = 8 MHz (in WIT state), functions except timer 1 disabled, Output transistors "off" f(XIN) = 2 MHz, VCC = 2.4 V (in WIT state), functions except timer 1 disabled, Output transistors "off" On-chip oscillator operation mode, VCC = 5V (in WIT state), functions except timer 1 disabled, Output transistors "off" Increment when A/D conversion is executed f(XIN) = 8 MHz, VCC = 5 V All oscillation stopped Ta = 25 C (in STP state) Ta = 85 C Output transistors "off" High-speed mode, f(XIN) = 8 MHz Mask ROM version Output transistors "off" High-speed mode, f(XIN) = 2 MHz, VCC = 2.4 V Output transistors "off" Double-speed mode, f(XIN) = 6 MHz Output transistors "off" Middle-speed mode, f(XIN) = 8 MHz Output transistors "off" On-chip oscillator operation mode, VCC = 5 V Output transistors "off" f(XIN) = 8 MHz (in WIT state), functions except timer 1 disabled, Output transistors "off" f(XIN) = 2 MHz, VCC = 2.4 V (in WIT state), functions except timer 1 disabled, Output transistors "off" On-chip oscillator operation mode, VCC = 5V (in WIT state), functions except timer 1 disabled, Output transistors "off" Increment when A/D conversion is executed f(XIN) = 8 MHz, VCC = 5 V All oscillation stopped Ta = 25 C (in STP state) Ta = 85 C Output transistors "off" Min. Typ. 5.0 0.5 6.0 2.0 350 1.6 Max. 8.0 1.5 10.0 5.0 1000 3.2 Unit mA mA mA mA A mA 0.2 mA 150 0.5 0.1 450 A mA 1.0 10 6.5 1.2 8.0 5.0 900 3.2 A A mA mA mA mA A mA 3.5 0.4 4.5 2.0 300 1.6 0.2 mA 150 0.5 0.1 450 A mA 1.0 10 A A Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-17 APPENDIX 7540 Group 3.1 Electrical characteristics (4) A/D Converter Characteristics (Extended operating temperature version) Table 3.1.18 A/D Converter characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol -- -- -- VOT One Time PROM version VFST Resolution Linearity error Differential nonlinear error Zero transition voltage Full scale transition voltage Parameter Test conditions Limits Min. Typ. Max. 10 3 0.9 0 0 5105 3060 5 3 5115 3069 55 150 70 20 15 5125 3075 122 200 120 5.0 10 3 1.5 0 0 5105 3060 15 9 5125 3075 55 150 70 35 21 5150 3090 122 200 120 5.0 Unit Bits LSB LSB mV mV mV mV tc(XIN) k A A Bits LSB LSB mV mV mV mV tc(XIN) k A A VCC = 2.7 to 5.5 V Ta = 25 C VCC = 2.7 to 5.5 V Ta = 25 C VCC = VREF = 5.12 V VCC = VREF = 3.072 V VCC = VREF = 5.12 V VCC = VREF = 3.072 V tCONV Conversion time RLADDER Ladder resistor IVREF Reference power source input current II(AD) -- -- -- VOT Mask ROM version VFST A/D port input current Resolution Linearity error Differential nonlinear error Zero transition voltage Full scale transition voltage VREF = 5.0 V VREF = 3.0 V 50 50 VCC = 2.7 to 5.5 V Ta = 25 C VCC = 2.7 to 5.5 V Ta = 25 C VCC = VREF = 5.12 V VCC = VREF = 3.072 V VCC = VREF = 5.12 V VCC = VREF = 3.072 V tCONV Conversion time RLADDER Ladder resistor IVREF Reference power source input current II(AD) A/D port input current VREF = 5.0 V VREF = 3.0 V 50 30 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-18 APPENDIX 7540 Group 3.1 Electrical characteristics (5) Timing Requirements (Extended operating temperature version) Table 3.1.19 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(CNTR1) tWH(CNTR1) tWL(CNTR1) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD1-SCLK1) th(SCLK1-RxD1) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SDATA2-SCLK2) th(SCLK2-SDATA2) Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0 input cycle time CNTR0, INT0, INT1, input "H" pulse width CNTR0, INT0, INT1, input "L" pulse width CNTR1 input cycle time CNTR1 input "H" pulse width CNTR1 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input "H" pulse width (Note) Serial I/O1 clock input "L" pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 input set up time Serial I/O2 input hold time Min. 2 125 50 50 200 80 80 2000 800 800 800 370 370 220 100 1000 400 400 200 200 Limits Typ. Max. s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to "1" (clock synchronous serial I/O1 is selected). When bit 6 of the serial I/O1 control register is "0" (clock asynchronous serial I/O1 is selected), the rating values are divided by 4. Table 3.1.20 Timing requirements (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(CNTR1) tWH(CNTR1) tWL(CNTR1) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD1-SCLK1) th(SCLK1-RxD1) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SDATA2-SCLK2) th(SCLK2-SDATA2) Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0 input cycle time CNTR0, INT0, INT1, input "H" pulse width CNTR0, INT0, INT1, input "L" pulse width CNTR1 input cycle time CNTR1 input "H" pulse width CNTR1 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input "H" pulse width (Note) Serial I/O1 clock input "L" pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 input set up time Serial I/O2 input hold time Min. 2 250 100 100 500 230 230 4000 1600 1600 2000 950 950 400 200 2000 950 950 400 400 Limits Typ. Max. s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to "1" (clock synchronous serial I/O1 is selected). When bit 6 of the serial I/O1 control register is "0" (clock asynchronous serial I/O1 is selected), the rating values are divided by 4. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-19 APPENDIX 7540 Group 3.1 Electrical characteristics (6) Switching Characteristics (Extended operating temperature version) Table 3.1.21 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1-TxD1) tv(SCLK1-TxD1) tr(SCLK1) tf(SCLK1) tWH(SCLK2) tWL(SCLK2) td(SCLK2-SDATA2) tv(SCLK2-SDATA2) tr(SCLK2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) Limits Min. tC(SCLK1)/2-30 tC(SCLK1)/2-30 140 -30 30 30 tC(SCLK2)/2-30 tC(SCLK2)/2-30 140 0 30 10 10 30 30 30 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1: Pin XOUT is excluded. Table 3.1.22 Switching characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = -40 to 85 C, unless otherwise noted) Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1-TxD1) tv(SCLK1-TxD1) tr(SCLK1) tf(SCLK1) tWH(SCLK2) tWL(SCLK2) td(SCLK2-SDATA2) tv(SCLK2-SDATA2) tr(SCLK2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) Limits Min. tC(SCLK1)/2-50 tC(SCLK1)/2-50 350 -30 50 50 tC(SCLK2)/2-50 tC(SCLK2)/2-50 350 0 50 50 50 50 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 20 20 Note 1: Pin XOUT is excluded. Measured output pin 100 pF /// CMOS output Fig. 3.1.3 Switching characteristics measurement circuit diagram (Extended operating temperature) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-20 APPENDIX 7540 Group 3.1 Electrical characteristics tC(CNTR0) tWH(CNTR0) tWL(CNTR0) 0.2VCC CNTR0 0.8VCC tC(CNTR1) tWH(CNTR1) tWL(CNTR1) 0.2VCC CNTR1 0.8VCC tWH(CNTR0) tWL(CNTR0) 0.2VCC INT0, INT1 0.8VCC tW(RESET) RESET 0.2VCC 0.8VCC tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC XIN 0.8VCC tf tWL(SCLK1) 0.2VCC tC(SCLK1) tr 0.8VCC tWH(SCLK1) SCLK1 tsu(RxD1-SCLK1) th(SCLK1-RxD1) RXD1 (at receive) td(SCLK1-TxD1) 0.8VCC 0.2VCC tv(SCLK1-TxD1) TXD1 (at transmit) tf tWL(SCLK2) 0.2VCC tC(SCLK2) tr 0.8VCC tWH(SCLK2) SCLK2 tsu(SDATA2-SCLK2) th(SCLK2-SDATA2) SDATA2 (at receive) td(SCLK2-SDATA2) 0.8VCC 0.2VCC tv(SCLK2-SDATA2) SDATA2 (at transmit) Fig. 3.1.4 Timing chart (Extended operating temperature version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-21 APPENDIX 7540 Group 3.1 Electrical characteristics 3.1.3 7540Group (Extended operating temperature 125 C version) Applied to: M37540M2V-XXXFP/GP, M37540M4V-XXXFP/GP, M37540E8V-XXXFP/GP (1) Absolute Maximum Ratings (Extended operating temperature 125 C version) Table 3.1.23 Absolute maximum ratings Symbol VCC VI VI VO Pd Topr Tstg Parameter Power source voltage Input voltage P00-P07, P10-P14, P20-P27, P30-P37, VREF Input voltage RESET, XIN, CNVSS Output voltage P00-P07, P10-P14, P20-P27, P30-P37, XOUT Power dissipation Operating temperature Storage temperature Conditions Ratings -0.3 to 6.5 (Note 1) -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 300 (Note 2) -40 to 125 (Note 3) -65 to 150 Unit V V V V mW C C All voltages are based on VSS. Output transistors are cut off. Ta = 25C Notes 1: This is the rating value for the Mask ROM version. The rating value for the One Time PROM version is -0.3 to 7.0 V. 2: 200 mW for the 32P6U package product. 3: In this version, the operating temperature range and total time are limited as follows; 55 C to 85 C: within total 6000 hours, 85 C to 125 C: within total 1000 hours. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-22 APPENDIX 7540 Group 3.1 Electrical characteristics (2) Recommended Operating Conditions (Extended operating temperature 125 C version) Table 3.1.24 Recommended operating conditions (1) (VCC = 2.4 to 5.5 V, Ta = -40 to 125 C, unless otherwise noted) Symbol VCC Power source voltage (ceramic) Parameter f(XIN) = 8 MHz (High-, Middle-speed mode) f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 4 MHz (Double-speed mode) f(XIN) = 2 MHz (Double-speed mode) f(XIN) = 4 MHz (High-, Middle-speed mode) f(XIN) = 2 MHz (High-, Middle-speed mode) Limits Min. 4.0 2.4 4.0 2.4 4.0 2.4 2.0 0.8VCC 2.0 0.8VCC 0 0 0 0 Typ. 5.0 5.0 5.0 5.0 5.0 5.0 0 Max. 5.5 5.5 5.5 5.5 5.5 5.5 VCC VCC VCC VCC 0.3VCC 0.8 0.2VCC 0.16VCC -80 80 60 -40 40 30 Unit V V V V V V V V V V V V V V V mA mA mA mA mA mA Power source voltage (RC) VSS VREF VIH VIH VIH VIL VIL VIL VIL IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) Power source voltage Analog reference voltage "H" input voltage P00-P07, P10-P14, P20-P27, P30-P37 "H" input voltage (TTL input level selected) P10, P12, P13, P36, P37 (Note 1) "H" input voltage RESET, XIN "L" input voltage P00-P07, P10-P14, P20-P27, P30-P37 "L" input voltage (TTL input level selected) P10, P12, P13, P36, P37 (Note 1) "L" input voltage RESET, CNVSS "L" input voltage XIN "H" total peak output current (Note 2) P00-P07, P10-P14, P20-P27, P30-P37 "L" total peak output current (Note 2) P00-P07, P10-P14, P20-P27, P37 "L" total peak output current (Note 2) P30-P36 "H" total average output current (Note 2) P00-P07, P10-P14, P20-P27, P30-P37 "L" total average output current (Note 2) P00-P07, P10-P14, P20-P27, P37 "L" total average output current (Note 2) P30-P36 Note 1: Vcc = 4.0 to 5.5V 2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-23 APPENDIX 7540 Group 3.1 Electrical characteristics Table 3.1.25 Recommended operating conditions (2) (VCC = 2.4 to 5.5 V, Ta = -40 to 125 C, unless otherwise noted) Symbol IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN) Parameter Limits Min. Typ. Max. -10 10 30 -5 5 15 4 2 8 4 4 2 Unit mA mA mA mA mA mA MHz MHz MHz MHz MHz MHz "H" peak output current (Note 1) P00-P07, P10-P14, P20-P27, P30-P37 "L" peak output current (Note 1) P00-P07, P10-P14, P20-P27, P37 "L" peak output current (Note 1) P30-P36 "H" average output current (Note 2) P00-P07, P10-P14, P20-P27, P30-P37 "L" average output current (Note 2) P00-P07, P10-P14, P20-P27, P37 "L" average output current (Note 2) P30-P36 Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V at ceramic oscillation or external clock input High-, Middle-speed mode Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V at ceramic oscillation or external clock input High-, Middle-speed mode Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V at RC oscillation High-, Middle-speed mode Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V at RC oscillation High-, Middle-speed mode Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50 %. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-24 APPENDIX 7540 Group 3.1 Electrical characteristics (3) Electrical Characteristics (Extended operating temperature 125 C version) Table 3.1.26 Electrical characteristics (1) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = -40 to 125 C, unless otherwise noted) Limits Symbol VOH Parameter "H" output voltage P00-P07, P10-P14, P20-P27, P30-P37 (Note 1) Test conditions IOH = -5 mA VCC = 4.0 to 5.5 V IOH = -1.0 mA VCC = 2.4 to 5.5 V IOL = 5 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 2.4 to 5.5 V IOL = 15 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 10 mA VCC = 2.4 to 5.5 V Min. VCC-1.5 VCC-1.0 1.5 0.3 1.0 2.0 0.3 1.0 0.4 Typ. Max. Unit V V V V V V V V V VOL "L" output voltage P00-P07, P10-P14, P20-P27, P37 VOL "L" output voltage P30-P36 VT+-VT- VT+-VT- VT+-VT- IIH Hysteresis CNTR0, CNTR1, INT0, INT1(Note 2) P00-P07 (Note 3) Hysteresis RXD, SCLK1, SCLK2, SDATA2 (Note 2) Hysteresis RESET "H" input current P00-P07, P10-P14, P20-P27, P30-P37 "H" input current RESET "H" input current XIN "L" input current P00-P07, P10-P14, P20-P27, P30-P37 "L" input current RESET, CNVSS "L" input current XIN "L" input current P00-P07, P30-P37 RAM hold voltage On-chip oscillator oscillation frequency Oscillation stop detection circuit detection frequency 0.5 0.5 VI = VCC (Pin floating. Pull up transistors "off") VI = VCC VI = VCC VI = VSS (Pin floating. Pull up transistors "off") VI = VSS VI = VSS VI = VSS (Pull up transistors "on") When clock stopped VCC = 5.0 V, Ta = 25 C VCC = 5.0 V, Ta = 25 C -4.0 -0.2 2.0 1000 62.5 -0.5 5.5 3000 187.5 4.0 -5.0 5.0 V V A A A A A A mA V kHz kHz IIH IIH IIL 5.0 IIL IIL IIL VRAM ROSC DOSC -5.0 2000 125 Notes 1: P11 is measured when the P11/TXD1 P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: RXD1, SCLK1, SCLK2, SDATA2, INT0, and INT1 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to "0" (CMOS level). 3: It is available only when operating key-on wake up. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-25 APPENDIX 7540 Group 3.1 Electrical characteristics Table 3.1.27 Electrical characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = -40 to 125 C, unless otherwise noted) Limits Symbol ICC Test conditions One Time PROM version High-speed mode, f(XIN) = 8 MHz Output transistors "off" High-speed mode, f(XIN) = 2 MHz, VCC = 2.4 V Output transistors "off" Middle-speed mode, f(XIN) = 8 MHz, Output transistors "off" On-chip oscillator operation mode, VCC = 5 V Output transistors "off" f(XIN) = 8 MHz (in WIT state), functions except timer 1 disabled, Output transistors "off" f(XIN) = 2 MHz, VCC = 2.4 V (in WIT state), functions except timer 1 disabled, Output transistors "off" On-chip oscillator operation mode, VCC = 5V (in WIT state), functions except timer 1 disabled, Output transistors "off" Increment when A/D conversion is executed f(XIN) = 8 MHz, VCC = 5 V Ta = 25 C All oscillation stopped (in STP state) Ta = 125 C Output transistors "off" Mask ROM version High-speed mode, f(XIN) = 8 MHz Output transistors "off" High-speed mode, f(XIN) = 2 MHz, VCC = 2.4 V Output transistors "off" Middle-speed mode, f(XIN) = 8 MHz, Output transistors "off" On-chip oscillator operation mode, VCC = 5 V Output transistors "off" f(XIN) = 8 MHz (in WIT state), functions except timer 1 disabled, Output transistors "off" f(XIN) = 2 MHz, VCC = 2.4 V (in WIT state), functions except timer 1 disabled, Output transistors "off" On-chip oscillator operation mode, VCC = 5V (in WIT state), functions except timer 1 disabled, Output transistors "off" Increment when A/D conversion is executed f(XIN) = 8 MHz, VCC = 5 V All oscillation stopped Ta = 25 C (in STP state) Ta = 125 C Output transistors "off" Min. Typ. 5.0 0.5 2.0 350 1.6 Max. 8.0 1.5 5.0 1000 3.2 Unit mA mA mA A mA 0.2 mA 150 0.5 0.1 450 A mA 1.0 50 6.5 1.2 5.0 900 3.2 A A mA mA mA A mA 3.5 0.4 2.0 300 1.6 0.2 mA 150 0.5 0.1 450 A mA 1.0 50 A A Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-26 APPENDIX 7540 Group 3.1 Electrical characteristics (4) A/D Converter Characteristics (Extended operating temperature 125 C version) Table 3.1.28 A/D Converter characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -40 to 125 C, unless otherwise noted) Symbol -- -- -- VOT One Time PROM version VFST Resolution Linearity error Differential nonlinear error Zero transition voltage Full scale transition voltage Parameter Test conditions Limits Min. Typ. Max. 10 3 0.9 0 0 5105 3060 5 3 5115 3069 55 150 70 20 15 5125 3075 122 200 120 7.0 10 3 1.5 0 0 5105 3060 15 9 5125 3075 55 150 70 35 21 5150 3090 122 200 120 7.0 Unit Bits LSB LSB mV mV mV mV tc(XIN) k A A Bits LSB LSB mV mV mV mV tc(XIN) k A A VCC = 2.7 to 5.5 V Ta = 25 C VCC = 2.7 to 5.5 V Ta = 25 C VCC = VREF = 5.12 V VCC = VREF = 3.072 V VCC = VREF = 5.12 V VCC = VREF = 3.072 V tCONV Conversion time RLADDER Ladder resistor IVREF Reference power source input current II(AD) -- -- -- VOT Mask ROM version VFST A/D port input current Resolution Linearity error Differential nonlinear error Zero transition voltage Full scale transition voltage VREF = 5.0 V VREF = 3.0 V 50 30 VCC = 2.7 to 5.5 V Ta = 25 C VCC = 2.7 to 5.5 V Ta = 25 C VCC = VREF = 5.12 V VCC = VREF = 3.072 V VCC = VREF = 5.12 V VCC = VREF = 3.072 V tCONV Conversion time RLADDER Ladder resistor IVREF Reference power source input current II(AD) A/D port input current VREF = 5.0 V VREF = 3.0 V 50 30 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-27 APPENDIX 7540 Group 3.1 Electrical characteristics (5) Timing Requirements (Extended operating temperature 125 C version) Table 3.1.29 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 125 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(CNTR1) tWH(CNTR1) tWL(CNTR1) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD1-SCLK1) th(SCLK1-RxD1) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SDATA2-SCLK2) th(SCLK2-SDATA2) Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0 input cycle time CNTR0, INT0, INT1, input "H" pulse width CNTR0, INT0, INT1, input "L" pulse width CNTR1 input cycle time CNTR1 input "H" pulse width CNTR1 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input "H" pulse width (Note) Serial I/O1 clock input "L" pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 input set up time Serial I/O2 input hold time Min. 2 125 50 50 200 80 80 2000 800 800 800 370 370 220 100 1000 400 400 200 200 Limits Typ. Max. s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to "1" (clock synchronous serial I/O1 is selected). When bit 6 of the serial I/O1 control register is "0" (clock asynchronous serial I/O1 is selected), the rating values are divided by 4. Table 3.1.30 Timing requirements (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = -40 to 125 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(CNTR1) tWH(CNTR1) tWL(CNTR1) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD1-SCLK1) th(SCLK1-RxD1) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SDATA2-SCLK2) th(SCLK2-SDATA2) Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0 input cycle time CNTR0, INT0, INT1, input "H" pulse width CNTR0, INT0, INT1, input "L" pulse width CNTR1 input cycle time CNTR1 input "H" pulse width CNTR1 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input "H" pulse width (Note) Serial I/O1 clock input "L" pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 input set up time Serial I/O2 input hold time Min. 2 250 100 100 500 230 230 4000 1600 1600 2000 950 950 400 200 2000 950 950 400 400 Limits Typ. Max. s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to "1" (clock synchronous serial I/O1 is selected). When bit 6 of the serial I/O1 control register is "0" (clock asynchronous serial I/O1 is selected), the rating values are divided by 4. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-28 APPENDIX 7540 Group 3.1 Electrical characteristics (6) Switching Characteristics (Extended operating temperature 125 C version) Table 3.1.30 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -40 to 125 C, unless otherwise noted) Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1-TxD1) tv(SCLK1-TxD1) tr(SCLK1) tf(SCLK1) tWH(SCLK2) tWL(SCLK2) td(SCLK2-SDATA2) tv(SCLK2-SDATA2) tr(SCLK2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) Limits Min. tC(SCLK1)/2-50 tC(SCLK1)/2-50 140 -30 30 30 tC(SCLK2)/2-50 tC(SCLK2)/2-50 140 0 30 30 30 30 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 Note 1: Pin XOUT is excluded. Table 3.1.31 Switching characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = -40 to 125 C, unless otherwise noted) Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1-TxD1) tv(SCLK1-TxD1) tr(SCLK1) tf(SCLK1) tWH(SCLK2) tWL(SCLK2) td(SCLK2-SDATA2) tv(SCLK2-SDATA2) tr(SCLK2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time Serial I/O1 output valid time Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) Limits Min. tC(SCLK1)/2-80 tC(SCLK1)/2-80 350 -30 50 50 tC(SCLK2)/2-80 tC(SCLK2)/2-80 350 0 50 50 50 50 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 20 20 Note 1: Pin XOUT is excluded. Measured output pin 100 pF /// CMOS output Fig. 3.1.5 Switching characteristics measurement circuit diagram (Extended operating temperature 125 C version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-29 APPENDIX 7540 Group 3.1 Electrical characteristics tC(CNTR0) tWH(CNTR0) tWL(CNTR0) 0.2VCC CNTR0 0.8VCC tC(CNTR1) tWH(CNTR1) tWL(CNTR1) 0.2VCC CNTR1 0.8VCC tWH(CNTR0) tWL(CNTR0) 0.2VCC INT0, INT1 0.8VCC tW(RESET) RESET 0.2VCC 0.8VCC tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC XIN 0.8VCC tf tWL(SCLK1) 0.2VCC tC(SCLK1) tr 0.8VCC tWH(SCLK1) SCLK1 tsu(RxD1-SCLK1) th(SCLK1-RxD1) RXD1 (at receive) td(SCLK1-TxD1) 0.8VCC 0.2VCC tv(SCLK1-TxD1) TXD1 (at transmit) tf tWL(SCLK2) 0.2VCC tC(SCLK2) tr 0.8VCC tWH(SCLK2) SCLK2 tsu(SDATA2-SCLK2) th(SCLK2-SDATA2) SDATA2 (at receive) td(SCLK2-SDATA2) 0.8VCC 0.2VCC tv(SCLK2-SDATA2) SDATA2 (at transmit) Fig. 3.1.6 Timing chart (Extended operating temperature 125 C version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-30 APPENDIX 7540 Group 3.2 Typical characteristics 3.2 Typical characteristics Standard characteristics described below are just examples of the 7540 Group's characteristics and are not guaranteed. For rated values, refer to "3.1 Electrical characteristics". 3.2.1 Mask ROM version (1) Power source current characteristic example (VCC-ICC characteristics) Measuring condition: When system is operating in double-speed mode (A/D conversion not executed), Ta = 25 C, Ceramic oscillation f(XIN) = 6 MHz 6 Power source current Icc [mA] f(XIN) = 4 MHz 4 f(XIN) = 2 MHz 2 f(XIN) = 1 MHz 0 2 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.1 VCC-ICC characteristics (in double-speed mode: Mask ROM version) Measuring condition: When system is operating in high-speed mode (A/D conversion not executed), Ta = 25 C, Ceramic oscillation 5 Power source current Icc [mA] f(XIN) = 8 MHz 4 3 2 1 0 2 3 4 5 6 f(XIN) = 4 MHz f(XIN) = 2 MHz Power source voltage Vcc [V] Fig. 3.2.2 VCC-ICC characteristics (in high-speed mode: Mask ROM version) Measuring condition: When system is operating in middle-speed mode (A/D conversion not executed), Ta = 25 C, Ceramic oscillation 3 Power source current Icc [mA] f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 2 MHz 2 1 0 2 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.3 VCC-ICC characteristics (in middle-speed mode: Mask ROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-31 APPENDIX 7540 Group 3.2 Typical characteristics Measuring condition: At WIT instruction execution (at wait), Ta = 25 C, Ceramic oscillation Power source current Icc [mA] 3 f(XIN) = 8 MHz 2 f(XIN) = 6 MHz f(XIN) = 4 MHz 1 0 2 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.4 VCC-ICC characteristics (at WIT instruction execution: Mask ROM version) Measuring condition: At STP instruction execution (at stop), Ta = 25 C, On-chip oscillator stop Power source current Icc [nA] 1.5 1.0 0.5 0.0 2 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.5 VCC-ICC characteristics (at STP instruction execution: Mask ROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-32 APPENDIX 7540 Group 3.2 Typical characteristics Measuring condition: A/D conversion executed/not executed (f(XIN) = 8 MHz in high-speed mode), Ta = 25 C, Ceramic oscillation Power source current Icc [mA] 8 6 During A/D conversion 4 During not A/D conversion 2 0 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.6 VCC-ICC characteristics (addition when operating A/D conversion, f(XIN) = 8 MHz in highspeed mode: Mask ROM version) Measuring condition: A/D conversion executed/not executed (f(XIN) = 6 MHz in double-speed mode), Ta = 25 C, Ceramic oscillation Power source current Icc [mA] 8 During A/D conversion 6 4 During not A/D conversion 2 0 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.7 VCC-ICC characteristics (addition when operating A/D conversion, f(XIN) = 6 MHz in doublespeed mode: Mask ROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-33 APPENDIX 7540 Group 3.2 Typical characteristics Measuring condition: When system is operating by on-chip oscillator (A/D conversion not executed), Ceramic oscillation stop Power source current Icc [A] 600 Ta = -45 C Ta = -25 C 400 Ta = 25 C Ta = 90 C Ta = 130 C 200 0 2 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.8 VCC-ICC characteristics (When system is operating by on-chip oscillator, Ceramic oscillation stop: Mask ROM version) Measuring condition: When system is operating by on-chip oscillator, at WIT instruction execution Ceramic oscillation stop 300 Power source current Icc [A] Ta = -45 C 200 Ta = -25 C Ta = 25 C Ta = 90 C Ta = 130 C 100 0 2 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.9 VCC-ICC characteristics (When system is operating by on-chip oscillator, at WIT instruction execution, Ceramic oscillation stop: Mask ROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-34 APPENDIX 7540 Group 3.2 Typical characteristics (2) Power source current characteristic example (f(XIN)-ICC characteristics) Measuring condition: When system is operating in double-speed mode (A/D conversion not executed), Ta = 25 C, Ceramic oscillation 5 Power source current Icc [mA] VCC = 5.0 V 4 3 2 1 0 1 2 3 4 5 6 VCC = 3.0 V Oscillation frequency f(XIN) [MHz] Fig. 3.2.10 f(XIN)-ICC characteristics (in double-speed mode: Mask ROM version) Measuring condition: When system is operating in high-speed mode (A/D conversion not executed), Ta = 25 C, Ceramic oscillation 4 Power source current Icc [mA] VCC = 5.0 V 3 2 VCC = 3.0 V 1 0 2 3 4 5 6 7 8 Oscillation frequency f(XIN) [MHz] Fig. 3.2.11 f(XIN)-ICC characteristics (in high-speed mode: Mask ROM version) Measuring condition: When system is operating in middle-speed mode (A/D conversion not executed), Ta = 25 C, Ceramic oscillation 2.5 2.0 1.5 1.0 Power source current Icc [mA] VCC = 5.0 V VCC = 3.0 V 0.5 0.0 2 3 4 5 6 7 8 Oscillation frequency f(XIN) [MHz] Fig. 3.2.12 f(XIN)-ICC characteristics (in middle-speed mode: Mask ROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-35 APPENDIX 7540 Group 3.2 Typical characteristics Measuring condition: At WIT instruction execution, Ta = 25 C, Ceramic oscillation Power source current Icc [mA] 2.0 1.5 VCC = 5.0 V 1.0 0.5 VCC = 3.0 V 0.0 1 2 3 4 5 6 7 8 Oscillation frequency f(XIN) [MHz] Fig. 3.2.13 f(XIN)-ICC characteristics (at WIT instruction execution: Mask ROM version) (3) Power source current characteristic example (Ta-ICC characteristics) Measuring condition: When system is operating by on-chip oscillator (A/D conversion not executed), Ceramic oscillation stop 400 Power source current Icc [A] 300 VCC = 5.0 V 200 100 VCC = 3.0 V 0 -50 -25 0 25 50 75 100 125 150 Operating temperature range [C] Fig. 3.2.14 Ta-ICC characteristics (When system is operating by on-chip oscillator, Ceramic oscillation stop: Mask ROM version) Measuring condition: When system is operating by on-chip oscillator, at WIT instruction execution, Ceramic oscillation stop Power source current Icc [A] 200 150 VCC = 5.0 V 100 50 VCC = 3.0 V 0 -50 -25 0 25 50 75 100 125 150 Operating temperature range Ta [C] Fig. 3.2.15 Ta-ICC characteristics (When system is operating by on-chip oscillator, at WIT instruction execution, Ceramic oscillation stop: Mask ROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-36 APPENDIX 7540 Group 3.2 Typical characteristics (4) Port typical characteristic example (VCC-VIHL characteristics) Measuring condition: VCC-VIHL characteristics of I/O port (CMOS), VCC = 5.0 V, Ta = 25 C (same characteristics pins: P01-P07, P11, P20-P27, P30-P35) 5 Input voltage VIHL [V] 4 3 2 1 0 2 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.16 VCC-VIHL characteristics (I/O port (CMOS): Mask ROM version) Measuring condition: VCC-VIHL characteristics of I/O port (TTL), VCC = 5.0 V, Ta = 25 C (same characteristics pins: P10, P12, P13, P36, P37) 5 4 Input voltage VIHL [V] 3 2 1 0 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.17 VCC-VIHL characteristics (I/O port (TTL): Mask ROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-37 APPENDIX 7540 Group 3.2 Typical characteristics Measuring condition: VCC-VIHL characteristics of RESET pin, VCC = 5.0 V, Ta = 25 C 5 Input voltage VIHL [V] 4 "H" input voltage (VIH) 3 2 1 0 2 3 4 5 6 "L" input voltage (VIL) Power source voltage Vcc [V] Fig. 3.2.18 VCC-VIHL characteristics (RESET pin: Mask ROM version) Measuring condition: VCC-VIHL characteristics of XIN pin, VCC = 5.0 V, Ta = 25 C 5 Input voltage VIHL [V] 4 3 2 1 0 2 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.19 VCC-VIHL characteristics (XIN pin: Mask ROM version) Measuring condition: VCC-VIL characteristics of CNVSS pin, VCC = 5.0 V, Ta = 25 C 5 Input voltage VIL [V] 4 3 2 1 0 2 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.20 VCC-VIL characteristics (CNVSS pin: Mask ROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-38 APPENDIX 7540 Group 3.2 Typical characteristics Measuring condition: VCC-HYS characteristics of RESET pin, VCC = 5.0 V, Ta = 25 C 1.0 0.8 Hysteresis HYS [V] 0.6 0.4 0.2 0.0 2 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.21 VCC-HYS characteristics (RESET pin: Mask ROM version) Measuring condition: VCC-HYS characteristics of SIO pin, VCC = 5.0 V, Ta = 25 C (same characteristics pins: RxD1, SCLK1, SCLK2, SDATA2) 1.0 Hysteresis HYS [V] 0.8 0.6 0.4 0.2 0.0 2 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.22 VCC-HYS characteristics (SIO pin: Mask ROM version) Measuring condition: VCC-HYS characteristics of INT pin, VCC = 5.0 V, Ta = 25 C (same characteristics pins: CNTR0, CNTR1, INT0, INT1, P00-P07) Hysteresis HYS [V] 1.0 0.8 0.6 0.4 0.2 0.0 2 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.23 VCC-HYS characteristics (INT pin: Mask ROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-39 APPENDIX 7540 Group 3.2 Typical characteristics (5) Port typical characteristic example (VOH-IOH characteristics) Measuring condition: VOH-IOH characteristics of P-channel (normal port), VCC = 3.0 V (same characteristics pins: P00-P07, P10-P14, P20-P27, P30-P37) -15 "H" output current IOH [mA] Ta = -40 C Ta = 25 C Ta = 125 C -10 -5 0 0 1 2 3 "H" output voltage VOH [V] Fig. 3.2.24 VOH-IOH characteristics of P-channel (VCC = 3.0 V, normal port: Mask ROM version) Measuring condition: VOH-IOH characteristics of P-channel (normal port), VCC = 5.0 V (same characteristics pins: P00-P07, P10-P14, P20-P27, P30-P37) "H" output current IOH [mA] -40 Ta = -40 C -30 Ta = 25 C Ta = 125 C -20 -10 0 0 1 2 3 4 5 "H" output voltage VOH [V] Fig. 3.2.25 VOH-IOH characteristics of P-channel (VCC = 5.0 V, normal port: Mask ROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-40 APPENDIX 7540 Group 3.2 Typical characteristics (6) Port typical characteristic example (VOL-IOL characteristics) Measuring condition: VOL-IOL characteristics of N-channel (normal port), VCC = 3.0 V (same characteristics pins: P00-P07, P10-P14, P20-P27, P37) 25 "L" output current IOL [mA] Ta = -40 C 20 Ta = 25 C 15 Ta = 125 C 10 5 0 0 1 2 3 "L" output voltage VOL [V] Fig. 3.2.26 VOL-IOL characteristics of N-channel (VCC = 3.0 V, normal port: Mask ROM version) Measuring condition: VOL-IOL characteristics of N-channel (normal port), VCC = 5.0 V (same characteristics pins: P00-P07, P10-P14, P20-P27, P37) 60 Ta = -40 C "L" output current IOL [mA] 45 Ta = 25 C Ta = 125 C 30 15 0 0 1 2 3 4 5 "L" output voltage VOL [V] Fig. 3.2.27 VOL-IOL characteristics of N-channel (VCC = 5.0 V, normal port: Mask ROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-41 APPENDIX 7540 Group 3.2 Typical characteristics Measuring condition: VOL-IOL characteristics of N-channel (LED drive port), VCC = 3.0 V (same characteristics pins: P30-P36) 50 "L" output current IOL [mA] Ta = -40 C 40 Ta = 25 C 30 Ta = 125 C 20 10 0 0 1 2 3 "L" output voltage VOL [V] Fig. 3.2.28 VOL-IOL characteristics of N-channel (VCC = 3.0 V, LED drive port: Mask ROM version) Measuring condition: VOL-IOL characteristics of N-channel (LED drive port), VCC = 5.0 V (same characteristics pins: P30-P36) 100 Ta = -40 C "L" output current IOL [mA] 80 Ta = 25 C Ta = 125 C 60 40 20 0 0 1 2 3 4 5 "L" output voltage VOL [V] Fig. 3.2.29 VOL-IOL characteristics of N-channel (VCC = 5.0 V, LED drive port: Mask ROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-42 APPENDIX 7540 Group 3.2 Typical characteristics (7) Port typical characteristic example (VCC-IIL characteristics) Measuring condition: Port "L" input current when connecting pull-up transistor (same characteristics pins: P00-P07, P30-P37) -0.4 "L" output current IIL [mA] Ta = -45 C Ta = -25 C -0.3 Ta = 25 C Ta = 90 C -0.2 Ta = 130 C -0.1 0 2 3 4 5 6 Power source voltage VCC [V] Fig. 3.2.30 VCC-IIL characteristics (Port "L" input current when connecting pull-up transistor: Mask ROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-43 APPENDIX 7540 Group 3.2 Typical characteristics (8) Port typical characteristic example (VIN-II(AD) characteristics) Measuring condition: f(XIN) = 8 MHz in high-speed mode, VCC = 5.0 V, Ta = 25 C (same characteristics pins: P20-P27) Input current II(AD) [A] 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0 1 2 3 4 5 Input voltage VIN [V] Fig. 3.2.31 VIN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 8 MHz in high-speed mode: Mask ROM version) Measuring condition: f(XIN) = 6 MHz in double-speed mode, VCC = 5.0 V, Ta = 25 C (same characteristics pins: P20-P27) Input current II(AD) [A] 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0 1 2 3 4 5 Input voltage VIN [V] Fig. 3.2.32 VIN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 6 MHz in double-speed mode: Mask ROM version) Measuring condition: f(XIN) = 4 MHz in double-speed mode, VCC = 5.0 V, Ta = 25 C (same characteristics pins: P20-P27) Input current II(AD) [A] 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0 1 2 3 4 5 Input voltage VIN [V] Fig. 3.2.33 VIN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 4 MHz in double-speed mode: Mask ROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-44 APPENDIX 7540 Group 3.2 Typical characteristics (9) On-chip oscillator frequency typical characteristic example Measuring parameter: On-chip oscillator frequency On-chip oscillator frequency ROSC [MHz] 4 3 Ta = -45 C Ta = -25 C Ta = 25 C Ta = 90 C Ta = 130 C 2 1 0 2 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.34 VCC-ROSC characteristics (on-chip oscillator frequency: Mask ROM version) Measuring parameter: On-chip oscillator frequency On-chip oscillator frequency ROSC [MHz] 3 2 VCC = 5.0 V 1 VCC = 3.0 V 0 -60 -40 -20 0 20 40 60 80 100 120 140 Operating temperature range Ta [C] Fig. 3.2.35 Ta-ROSC characteristics (on-chip oscillator frequency: Mask ROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-45 APPENDIX 7540 Group 3.2 Typical characteristics (10) RC oscillation frequency typical characteristic example Measuring parameter: RC oscillation frequency Measuring condition: VCC = 5.0 V, Ta = 25 C, C = 33 pF 6 RC oscillation frequency f(XIN) [MHz] 5 4 3 2 1 0 0 10 20 30 40 50 External resistor R [k] Fig. 3.2.36 R-f(XIN) characteristics (RC oscillation frequency: Mask ROM version) Measuring parameter: RC oscillation frequency Measuring condition: VCC = 5.0 V, Ta = 25 C, R = 6.8 k (fixed) RC oscillation frequency f(XIN) [MHz] 5 4 3 2 1 0 0 10 20 30 40 50 60 External capacitor C [pF] Fig. 3.2.37 C-f(XIN) characteristics (RC oscillation frequency: Mask ROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-46 APPENDIX 7540 Group 3.2 Typical characteristics Measuring parameter: RC oscillation frequency Measuring condition: Ta = 25 C, f(XIN) 4 MHz (R = 5.1 k, C = 20 pF) 5 RC oscillation frequency f(XIN) [MHz] 4 3 2 1 0 2 3 4 5 6 Power source voltage VCC [V] Fig. 3.2.38 VCC-f(XIN) characteristics (RC oscillation frequency: Mask ROM version) Measuring parameter: RC oscillation frequency Measuring condition: f(XIN) 4 MHz (R = 5.1 k, C = 20 pF) 5.0 RC oscillation frequency f(XIN) [MHz] 4.5 VCC = 5.0 V 4.0 VCC = 3.0 V 3.5 3.0 -60 -40 -20 0 20 40 60 80 100 120 140 Operating temperature range Ta [C] Fig. 3.2.39 Ta-f(XIN) characteristics (RC oscillation frequency: Mask ROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-47 APPENDIX 7540 Group 3.2 Typical characteristics (11) A/D conversion typical characteristics example Definition of A/D conversion accuracy The A/D conversion accuracy is defined below (refer to Fig. 3.2.40). qRelative accuracy * Zero transition voltage (VOT) This means an analog input voltage when the actual A/D conversion output data changes from "0" to "1." * Full-scale transition voltage (VFST) This means an analog input voltage when the actual A/D conversion output data changes from "1023" to "1022." * Non-linearity error This means a deviation from the line between VOT and VFST of a converted value between VOT and VFST. * Differential non-linearity error This means a deviation from the input potential difference required to change a converted value between VOT and VFST by 1 LSB of the 1 LSB at the relative accuracy. qAbsolute accuracy This means a deviation from the ideal characteristics between 0 to VREF of actual A/D conversion characteristics. Output data Full-scale transition voltage (VFST) 1023 1022 Differential non-linearity error= c Non-linearity error= a [LSB] b-a a [LSB] b a n+1 n Actual A/D conversion characteristics c a: 1LSB at relative accuracy b: Vn+1-Vn c: Difference between the ideal Vn and actual Vn Ideal line of A/D conversion between V0 to V1022 1 0 V0 V1 Vn Vn+1 V1022 Zero transition voltage (V0T) Analog voltage VREF Fig. 3.2.40 Definition of A/D conversion accuracy Vn: Analog input voltage when the output data changes from "n" to "n + 1" (n = 0 to 1022) VFST - VOT 1022 VREF * 1 LSB at absolute accuracy 1024 * 1 LSB at relative accuracy Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z (V) (V) 3-48 APPENDIX 7540 Group 3.2 Typical characteristics A/D conversion accuracy typical characteristics-1 M37540M4-XXXFP A/D CONVERTER STEP WIDTH MEASUREMENT *VCC = 5.12 [V] *VREF = 5.12 [V] *XIN = 4 [MHz] *Temp. = 25 [C] *CPU mode = double-speed mode 15 ERROR/1LSB WIDTH [mV] *Zero transition voltage: 13.75 mV *Full-scale transition voltage: 5120.94 mV *Differential non-linearity error: -1.72 mV (-0.34 LSB) *Non-linearity error: -5.09 mV (-1.02 LSB) 10 5 Reference(ERROR(ABSOLUTE)) 1LSB WIDTH 0 0 -5 32 64 96 ERROR (LINEARITY) 128 160 192 224 256 -10 -15 15 ERROR/1LSB WIDTH [mV] 10 5 0 256 -5 288 320 352 384 416 448 480 512 -10 -15 15 ERROR/1LSB WIDTH [mV] 10 5 0 512 -5 544 576 608 640 672 704 736 768 -10 -15 15 ERROR/1LSB WIDTH [mV] 10 5 0 768 -5 800 832 864 896 928 960 992 1024 -10 -15 Fig. 3.2.41 A/D conversion accuracy typical characteristic example-1 (Mask ROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-49 APPENDIX 7540 Group 3.2 Typical characteristics A/D conversion accuracy typical characteristics-2 M37540M4-XXXFP A/D CONVERTER STEP WIDTH MEASUREMENT *VCC = 5.12 [V] *VREF = 5.12 [V] *XIN = 6 [MHz] *Temp. = 25 [C] *CPU mode = double-speed mode 15 ERROR/1LSB WIDTH [mV] Reference(ERROR(ABSOLUTE)) *Zero transition voltage: 14.38 mV *Full-scale transition voltage: 5121.88 mV *Differential non-linearity error: 1.41 mV (0.28 LSB) *Non-linearity error: -4.23 mV (-0.85 LSB) 10 5 1LSB WIDTH 0 0 -5 32 64 96 ERROR (LINEARITY) 128 160 192 224 256 -10 -15 15 ERROR/1LSB WIDTH [mV] 10 5 0 256 -5 288 320 352 384 416 448 480 512 -10 -15 15 ERROR/1LSB WIDTH [mV] 10 5 0 512 -5 544 576 608 640 672 704 736 768 -10 -15 15 ERROR/1LSB WIDTH [mV] 10 5 0 768 -5 800 832 864 896 928 960 992 1024 -10 -15 Fig. 3.2.42 A/D conversion accuracy typical characteristic example-2 (Mask ROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-50 APPENDIX 7540 Group 3.2 Typical characteristics A/D conversion accuracy typical characteristics-3 M37540M4-XXXFP A/D CONVERTER STEP WIDTH MEASUREMENT *VCC = 5.12 [V] *VREF = 5.12 [V] *XIN = 8 [MHz] *Temp. = 25 [C] *CPU mode = high-speed mode 30 ERROR/1LSB WIDTH [mV] *Zero transition voltage: 30.31 mV *Full-scale transition voltage: 5143.33 mV *Differential non-linearity error: 1.72 mV (0.34 LSB) *Non-linearity error: -7.64 mV (-1.53 LSB) 25 20 15 10 1LSB WIDTH Reference(ERROR(ABSOLUTE)) 5 0 0 -5 32 64 96 128 160 192 224 256 ERROR (LINEARITY) -10 30 ERROR/1LSB WIDTH [mV] 25 20 15 10 5 0 256 -5 288 320 352 384 416 448 480 512 -10 30 ERROR/1LSB WIDTH [mV] 25 20 15 10 5 0 512 -5 544 576 608 640 672 704 736 768 -10 30 ERROR/1LSB WIDTH [mV] 25 20 15 10 5 0 768 -5 800 832 864 896 928 960 992 1024 -10 Fig. 3.2.43 A/D conversion accuracy typical characteristic example-3 (Mask ROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-51 APPENDIX 7540 Group 3.2 Typical characteristics 3.2.2 One Time PROM version (1) Power source current characteristic example (VCC-ICC characteristics) Measuring condition: When system is operating in double-speed mode (A/D conversion not executed), Ta = 25 C, Ceramic oscillation 10 8 6 4 2 0 2 3 4 5 6 Power source current Icc [mA] f(XIN) = 6 MHz f(XIN) = 4 MHz f(XIN) = 2 MHz f(XIN) = 1 MHz Power source voltage Vcc [V] Fig. 3.2.44 VCC-ICC characteristics (in double-speed mode: One Time PROM version) Measuring condition: When system is operating in high-speed mode (A/D conversion not executed), Ta = 25 C, Ceramic oscillation 8 Power source current Icc [mA] f(XIN) = 8 MHz 6 4 f(XIN) = 4 MHz f(XIN) = 2 MHz 2 0 2 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.45 VCC-ICC characteristics (in high-speed mode: One Time PROM version) Measuring condition: When system is operating in middle-speed mode (A/D conversion not executed), Ta = 25 C, Ceramic oscillation 4 Power source current Icc [mA] f(XIN) = 8 MHz 3 f(XIN) = 4 MHz 2 f(XIN) = 2 MHz 1 0 2 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.46 VCC-ICC characteristics (in middle-speed mode: One Time PROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-52 APPENDIX 7540 Group 3.2 Typical characteristics Measuring condition: At WIT instruction execution (at wait), Ta = 25 C, Ceramic oscillation Power source current Icc [mA] 3 f(XIN) = 8 MHz 2 f(XIN) = 6 MHz 1 f(XIN) = 4 MHz 0 2 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.47 VCC-ICC characteristics (at WIT instruction execution: One Time PROM version) Measuring condition: At STP instruction execution (at stop), Ta = 25 C, On-chip oscillator stop Power source current Icc [nA] 3 2 1 0 2 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.48 VCC-ICC characteristics (at STP instruction execution: One Time PROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-53 APPENDIX 7540 Group 3.2 Typical characteristics Measuring condition: A/D conversion executed/not executed (f(XIN) = 8 MHz in high-speed mode), Ta = 25 C, Ceramic oscillation Power source current Icc [mA] 8 During A/D conversion 6 During not A/D conversion 4 2 0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Power source voltage Vcc [V] Fig. 3.2.49 VCC-ICC characteristics (addition when operating A/D conversion, f(XIN) = 8 MHz in highspeed mode: One Time PROM version) Measuring condition: A/D conversion executed/not executed (f(XIN) = 6 MHz in double-speed mode), Ta = 25 C, Ceramic oscillation Power source current Icc [mA] 10 During A/D conversion 8 6 4 2 0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 During not A/D conversion Power source voltage Vcc [V] Fig. 3.2.50 VCC-ICC characteristics (addition when operating A/D conversion, f(XIN) = 6 MHz in doublespeed mode: One Time PROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-54 APPENDIX 7540 Group 3.2 Typical characteristics Measuring condition: When system is operating by on-chip oscillator (A/D conversion not executed), Ceramic oscillation stop Power source current Icc [A] 800 Ta = -45 C 600 Ta = -25 C Ta = 25 C Ta = 90 C Ta = 130 C 400 200 0 2 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.51 VCC-ICC characteristics (When system is operating by on-chip oscillator, Ceramic oscillation stop: One Time PROM version) Measuring condition: When system is operating by on-chip oscillator, at WIT instruction execution Ceramic oscillation stop 300 Power source current Icc [A] Ta = -45 C 200 Ta = -25 C Ta = 25 C Ta = 90 C 100 Ta = 130 C 0 2 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.52 VCC-ICC characteristics (When system is operating by on-chip oscillator, at WIT instruction execution, Ceramic oscillation stop: One Time PROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-55 APPENDIX 7540 Group 3.2 Typical characteristics (2) Power source current characteristic example (f(XIN)-ICC characteristics) Measuring condition: When system is operating in double-speed mode (A/D conversion not executed), Ta = 25 C, Ceramic oscillation 8 Power source current Icc [mA] 6 VCC = 5.0 V 4 2 VCC = 3.0 V 0 1 2 3 4 5 6 Oscillation frequency f(XIN) [MHz] Fig. 3.2.53 f(XIN)-ICC characteristics (in double-speed mode: One Time PROM version) Measuring condition: When system is operating in high-speed mode (A/D conversion not executed), Ta = 25 C, Ceramic oscillation 6 Power source current Icc [mA] VCC = 5.0 V 4 2 VCC = 3.0 V 0 2 3 4 5 6 7 8 Oscillation frequency f(XIN) [MHz] Fig. 3.2.54 f(XIN)-ICC characteristics (in high-speed mode: One Time PROM version) Measuring condition: When system is operating in middle-speed mode (A/D conversion not executed), Ta = 25 C, Ceramic oscillation 3 Power source current Icc [mA] VCC = 5.0 V 2 1 VCC = 3.0 V 0 2 3 4 5 6 7 8 Oscillation frequency f(XIN) [MHz] Fig. 3.2.55 f(XIN)-ICC characteristics (in middle-speed mode: One Time PROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-56 APPENDIX 7540 Group 3.2 Typical characteristics Measuring condition: At WIT instruction execution, Ta = 25 C, Ceramic oscillation Power source current Icc [mA] 2.0 1.5 VCC = 5.0 V 1.0 0.5 VCC = 3.0 V 0.0 1 2 3 4 5 6 7 8 Oscillation frequency f(XIN) [MHz] Fig. 3.2.56 f(XIN)-ICC characteristics (at WIT instruction execution: One Time PROM version) (3) Power source current characteristic example (Ta-ICC characteristics) Measuring condition: When system is operating by on-chip oscillator (A/D conversion not executed), Ceramic oscillation stop 500 400 300 200 100 Power source current Icc [A] VCC = 5.0 V VCC = 3.0 V 0 -50 -25 0 25 50 75 100 125 150 Operating temperature range [C] Fig. 3.2.57 Ta-ICC characteristics (When system is operating by on-chip oscillator, Ceramic oscillation stop: One Time PROM version) Measuring condition: When system is operating by on-chip oscillator, at WIT instruction execution, Ceramic oscillation stop Power source current Icc [A] 200 150 VCC = 5.0 V 100 50 VCC = 3.0 V 0 -50 -25 0 25 50 75 100 125 150 Operating temperature range Ta [C] Fig. 3.2.58 Ta-ICC characteristics (When system is operating by on-chip oscillator, at WIT instruction execution, Ceramic oscillation stop: One Time PROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-57 APPENDIX 7540 Group 3.2 Typical characteristics (4) Port typical characteristic example (VCC-VIHL characteristics) Measuring condition: VCC-VIHL characteristics of I/O port (CMOS), VCC = 5.0 V, Ta = 25 C (same characteristics pins: P01-P07, P11, P20-P27, P30-P35) 5 Input voltage VIHL [V] 4 3 2 1 0 2 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.59 VCC-VIHL characteristics (I/O port (CMOS): One Time PROM version) Measuring condition: VCC-VIHL characteristics of I/O port (TTL), VCC = 5.0 V, Ta = 25 C (same characteristics pins: P10, P12, P13, P36, P37) 5 4 Input voltage VIHL [V] 3 2 1 0 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.60 VCC-VIHL characteristics (I/O port (TTL): One Time PROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-58 APPENDIX 7540 Group 3.2 Typical characteristics Measuring condition: VCC-VIHL characteristics of RESET pin, VCC = 5.0 V, Ta = 25 C 5 Input voltage VIHL [V] 4 "H" input voltage (VIH) 3 2 1 0 2 3 4 5 6 "L" input voltage (VIL) Power source voltage Vcc [V] Fig. 3.2.61 VCC-VIHL characteristics (RESET pin: One Time PROM version) Measuring condition: VCC-VIHL characteristics of XIN pin, VCC = 5.0 V, Ta = 25 C 5 Input voltage VIHL [V] 4 3 2 1 0 2 3 4 Power source voltage Vcc [V] 5 6 Fig. 3.2.62 VCC-VIHL characteristics (XIN pin: One Time PROM version) Measuring condition: VCC-VIL characteristics of CNVSS pin, VCC = 5.0 V, Ta = 25 C 5 Input voltage VIL [V] 4 3 2 1 0 2 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.63 VCC-VIL characteristics (CNVSS pin: One Time PROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-59 APPENDIX 7540 Group 3.2 Typical characteristics Measuring condition: VCC-HYS characteristics of RESET pin, VCC = 5.0 V, Ta = 25 C 1.0 0.8 Hysteresis HYS [V] 0.6 0.4 0.2 0.0 2 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.64 VCC-HYS characteristics (RESET pin: One Time PROM version) Measuring condition: VCC-HYS characteristics of SIO pin, VCC = 5.0 V, Ta = 25 C (same characteristics pins: RxD1, SCLK1, SCLK2, SDATA2) 1.0 Hysteresis HYS [V] 0.8 0.6 0.4 0.2 0.0 2 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.65 VCC-HYS characteristics (SIO pin: One Time PROM version) Measuring condition: VCC-HYS characteristics of INT pin, VCC = 5.0 V, Ta = 25 C (same characteristics pins: CNTR0, CNTR1, INT0, INT1, P00-P07) 1.0 Hysteresis HYS [V] 0.8 0.6 0.4 0.2 0.0 2 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.66 VCC-HYS characteristics (INT pin: One Time PROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-60 APPENDIX 7540 Group 3.2 Typical characteristics (5) Port typical characteristic example (VOH-IOH characteristics) Measuring condition: VOH-IOH characteristics of P-channel (normal port), VCC = 3.0 V (same characteristics pins: P00-P07, P10-P14, P20-P27, P30-P37) -15 "H" output current IOH [mA] Ta = 25 C -10 Ta = 125 C -5 0 0 1 2 3 "H" output voltage VOH [V] Fig. 3.2.67 VOH-IOH characteristics of P-channel (VCC = 3.0 V, normal port: One Time PROM version) Measuring condition: VOH-IOH characteristics of P-channel (normal port), VCC = 5.0 V (same characteristics pins: P00-P07, P10-P14, P20-P27, P30-P37) "H" output current IOH [mA] -50 Ta = -40 C -40 Ta = 25 C -30 Ta = 125 C -20 -10 0 0 1 2 3 4 5 "H" output voltage VOH [V] Fig. 3.2.68 VOH-IOH characteristics of P-channel (VCC = 5.0 V, normal port: One Time PROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-61 APPENDIX 7540 Group 3.2 Typical characteristics (6) Port typical characteristic example (VOL-IOL characteristics) Measuring condition: VOL-IOL characteristics of N-channel (normal port), VCC = 3.0 V (same characteristics pins: P00-P07, P10-P14, P20-P27, P37) 25 "L" output current IOL [mA] 20 Ta = 25 C 15 Ta = 125 C 10 5 0 0 1 2 3 "L" output voltage VOL [V] Fig. 3.2.69 VOL-IOL characteristics of N-channel (VCC = 3.0 V, normal port: One Time PROM version) Measuring condition: VOL-IOL characteristics of N-channel (normal port), VCC = 5.0 V (same characteristics pins: P00-P07, P10-P14, P20-P27, P37) 60 "L" output current IOL [mA] Ta = -40 C 45 Ta = 25 C Ta = 125 C 30 15 0 0 1 2 3 4 5 "L" output voltage VOL [V] Fig. 3.2.70 VOL-IOL characteristics of N-channel (VCC = 5.0 V, normal port: One Time PROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-62 APPENDIX 7540 Group 3.2 Typical characteristics Measuring condition: VOL-IOL characteristics of N-channel (LED drive port), VCC = 3.0 V (same characteristics pins: P30-P36) 40 "L" output current IOL [mA] Ta = 25 C 30 Ta = 125 C 20 10 0 0 1 2 3 "L" output voltage VOL [V] Fig. 3.2.71 VOL-IOL characteristics of N-channel (VCC = 3.0 V, LED drive port: One Time PROM version) Measuring condition: VOL-IOL characteristics of N-channel (LED drive port), VCC = 5.0 V (same characteristics pins: P30-P36) 100 Ta = -40 C Ta = 25 C "L" output current IOL [mA] 80 60 Ta = 125 C 40 20 0 0 1 2 3 4 5 "L" output voltage VOL [V] Fig. 3.2.72 VOL-IOL characteristics of N-channel (VCC = 5.0 V, LED drive port: One Time PROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-63 APPENDIX 7540 Group 3.2 Typical characteristics (7) Port typical characteristic example (VCC-IIL characteristics) Measuring condition: Port "L" input current when connecting pull-up transistor (same characteristics pins: P00-P07, P30-P37) "L" output current IIL [mA] -0.5 -0.4 Ta = -45 C Ta = -25 C Ta = 25 C -0.3 Ta = 90 C -0.2 Ta = 130 C -0.1 0 2 3 4 5 6 Power source voltage VCC [V] Fig. 3.2.73 VCC-IIL characteristics (Port "L" input current when connecting pull-up transistor: One Time PROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-64 APPENDIX 7540 Group 3.2 Typical characteristics (8) Port typical characteristic example (VIN-II(AD) characteristics) Measuring condition: f(XIN) = 8 MHz in high-speed mode, VCC = 5.0 V, Ta = 25 C (same characteristics pins: P20-P27) Input current II(AD) [A] 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0 1 2 3 4 5 Input voltage VIN [V] Fig. 3.2.74 VIN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 8 MHz in high-speed mode: One Time PROM version) Measuring condition: f(XIN) = 6 MHz in double-speed mode, VCC = 5.0 V, Ta = 25 C (same characteristics pins: P20-P27) Input current II(AD) [A] 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0 1 2 3 4 5 Input voltage VIN [V] Fig. 3.2.75 VIN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 6 MHz in double-speed mode: One Time PROM version) Measuring condition: f(XIN) = 4 MHz in double-speed mode, VCC = 5.0 V, Ta = 25 C (same characteristics pins: P20-P27) Input current II(AD) [A] 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0 1 2 3 4 5 Input voltage VIN [V] Fig. 3.2.76 VIN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 4 MHz in double-speed mode: One Time PROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-65 APPENDIX 7540 Group 3.2 Typical characteristics (9) On-chip oscillator frequency typical characteristic example Measuring parameter: On-chip oscillator frequency On-chip oscillator frequency ROSC [MHz] 4 Ta = -45 C 3 Ta = -25 C Ta = 25 C 2 Ta = 90 C Ta = 130 C 1 0 2 3 4 5 6 Power source voltage Vcc [V] Fig. 3.2.77 VCC-ROSC characteristics (on-chip oscillator frequency: One Time PROM version) Measuring parameter: On-chip oscillator frequency On-chip oscillator frequency ROSC [MHz] 4 3 VCC = 5.0 V 2 1 VCC = 3.0 V 0 -60 -40 -20 0 20 40 60 80 100 120 140 Operating temperature range Ta [C] Fig. 3.2.78 Ta-ROSC characteristics (on-chip oscillator frequency: One Time PROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-66 APPENDIX 7540 Group 3.2 Typical characteristics (10) RC oscillation frequency typical characteristic example Measuring parameter: RC oscillation frequency Measuring condition: VCC = 5.0 V, Ta = 25 C RC oscillation frequency f(XIN) [MHz] 6 C = 20 pF C = 33 pF 4 C = 47 pF 2 0 0 10 20 30 40 50 External resistor R [k] Fig. 3.2.79 R-f(XIN) characteristics (RC oscillation frequency: One Time PROM version) Measuring parameter: RC oscillation frequency Measuring condition: VCC = 5.0 V, Ta = 25 C RC oscillation frequency f(XIN) [MHz] 8 R = 5.1 k 6 4 R = 10 k R = 15 k 2 0 0 10 20 30 40 50 60 External capacitor C [pF] Fig. 3.2.80 C-f(XIN) characteristics (RC oscillation frequency: One Time PROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-67 APPENDIX 7540 Group 3.2 Typical characteristics Measuring parameter: RC oscillation frequency Measuring condition: Ta = 25 C, R = 5.1 k/C = 33 pF RC oscillation frequency f(XIN) [MHz] 5.0 4.0 3.0 2.0 1.0 0.0 2 3 4 5 6 Power source voltage VCC [V] Fig. 3.2.81 VCC-f(XIN) characteristics (RC oscillation frequency: One Time PROM version) Measuring parameter: RC oscillation frequency Measuring condition: R = 5.1 k, C = 33 pF RC oscillation frequency f(XIN) [MHz] 5.0 4.8 VCC = 5.0 V 4.6 VCC = 3.0 V 4.4 4.2 4.0 -60 -30 0 30 60 90 120 150 Operating temperature range Ta [C] Fig. 3.2.82 Ta-f(XIN) characteristics (RC oscillation frequency: One Time PROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-68 APPENDIX 7540 Group 3.2 Typical characteristics (11) A/D conversion typical characteristics example Definition of A/D conversion accuracy The A/D conversion accuracy is defined below (refer to Fig. 3.2.83). qRelative accuracy * Zero transition voltage (VOT) This means an analog input voltage when the actual A/D conversion output data changes from "0" to "1." * Full-scale transition voltage (VFST) This means an analog input voltage when the actual A/D conversion output data changes from "1023" to "1022." * Non-linearity error This means a deviation from the line between VOT and VFST of a converted value between VOT and VFST. * Differential non-linearity error This means a deviation from the input potential difference required to change a converted value between VOT and VFST by 1 LSB of the 1 LSB at the relative accuracy. qAbsolute accuracy This means a deviation from the ideal characteristics between 0 to VREF of actual A/D conversion characteristics. Output data Full-scale transition voltage (VFST) 1023 1022 Differential non-linearity error= c Non-linearity error= a [LSB] b-a a [LSB] b a n+1 n Actual A/D conversion characteristics c a: 1LSB at relative accuracy b: Vn+1-Vn c: Difference between the ideal Vn and actual Vn Ideal line of A/D conversion between V0 to V1022 1 0 V0 V1 Vn Vn+1 V1022 Zero transition voltage (V0T) Analog voltage VREF Fig. 3.2.83 Definition of A/D conversion accuracy Vn: Analog input voltage when the output data changes from "n" to "n + 1" (n = 0 to 1022) VFST - VOT 1022 VREF * 1 LSB at absolute accuracy 1024 * 1 LSB at relative accuracy Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z (V) (V) 3-69 APPENDIX 7540 Group 3.2 Typical characteristics A/D conversion accuracy typical characteristics-1 M37540E8FP A/D CONVERTER STEP WIDTH MEASUREMENT *VCC = 5.12 [V] *VREF = 5.12 [V] *XIN = 4 [MHz] *Temp. = 25 [C] *CPU mode = double-speed mode 10 ERROR/1LSB WIDTH [mV] 1LSB WIDTH *Zero transition voltage: 6.88 mV *Full-scale transition voltage: 5115.63 mV *Differential non-linearity error: -2.34 mV (-0.47 LSB) *Non-linearity error: -5.66 mV (-1.13 LSB) 5 Reference(ERROR(ABSOLUTE)) 0 0 -5 32 64 96 ERROR (LINEARITY) 128 160 192 224 256 -10 10 ERROR/1LSB WIDTH [mV] 5 0 256 -5 288 320 352 384 416 448 480 512 -10 10 ERROR/1LSB WIDTH [mV] 5 0 512 -5 544 576 608 640 672 704 736 768 -10 10 ERROR/1LSB WIDTH [mV] 5 0 768 -5 800 832 864 896 928 960 992 1024 -10 Fig. 3.2.84 A/D conversion accuracy typical characteristic example-1 (One Time PROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-70 APPENDIX 7540 Group 3.2 Typical characteristics A/D conversion accuracy typical characteristics-2 M37540E8FP A/D CONVERTER STEP WIDTH MEASUREMENT *VCC = 5.12 [V] *VREF = 5.12 [V] *XIN = 6 [MHz] *Temp. = 25 [C] *CPU mode = double-speed mode 10 ERROR/1LSB WIDTH [mV] 1LSB WIDTH *Zero transition voltage: 5.94 mV *Full-scale transition voltage: 5113.44 mV *Differential non-linearity error: 3.28 mV (0.66 LSB) *Non-linearity error: -4.91 mV (-0.98 LSB) 5 Reference(ERROR(ABSOLUTE)) 0 0 32 64 96 ERROR (LINEARITY) 128 160 192 224 256 -5 -10 10 ERROR/1LSB WIDTH [mV] 5 0 256 288 320 352 384 416 448 480 512 -5 -10 10 ERROR/1LSB WIDTH [mV] 5 0 512 544 576 608 640 672 704 736 768 -5 -10 10 ERROR/1LSB WIDTH [mV] 5 0 768 800 832 864 896 928 960 992 1024 -5 -10 Fig. 3.2.85 A/D conversion accuracy typical characteristic example-2 (One Time PROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-71 APPENDIX 7540 Group 3.2 Typical characteristics A/D conversion accuracy typical characteristics-3 M37540E8FP A/D CONVERTER STEP WIDTH MEASUREMENT *VCC = 5.12 [V] *VREF = 5.12 [V] *XIN = 8 [MHz] *Temp. = 25 [C] *CPU mode = high-speed mode 10 ERROR/1LSB WIDTH [mV] 1LSB WIDTH *Zero transition voltage: 5.63 mV *Full-scale transition voltage: 5115.31 mV *Differential non-linearity error: -2.66 mV (-0.53 LSB) *Non-linearity error: -5.99 mV (-1.20 LSB) 5 Reference(ERROR(ABSOLUTE)) 0 0 -5 32 64 96 ERROR (LINEARITY) 128 160 192 224 256 -10 10 ERROR/1LSB WIDTH [mV] 5 0 256 -5 288 320 352 384 416 448 480 512 -10 10 ERROR/1LSB WIDTH [mV] 5 0 512 -5 544 576 608 640 672 704 736 768 -10 10 ERROR/1LSB WIDTH [mV] 5 0 768 -5 800 832 864 896 928 960 992 1024 -10 Fig. 3.2.86 A/D conversion accuracy typical characteristic example-3 (One Time PROM version) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-72 APPENDIX 7540 Group 3.3 Notes on use 3.3 Notes on use 3.3.1 Notes on input and output ports Notes on using input and output ports are described below. (1) Notes in stand-by state In stand-by state* 1 for low-power dissipation, do not make input levels of an input port and an I/O port "undefined". Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a resistor. When determining a resistance value, note the following points: * External circuit * Variation of output levels during the ordinary operation When using a built-in pull-up resistor, note on varied current values: * When setting as an input port : Fix its input level * When setting as an output port : Prevent current from flowing out to external. q Reason The output transistor becomes the OFF state, which causes the ports to be the high-impedance state. Note that the level becomes "undefined" depending on external circuits. Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of a input port and an I/O port are "undefined". This may cause power source current. * 1 stand-by state : the stop mode by executing the STP instruction the wait mode by executing the WIT instruction (2) Modifying output data with bit managing instruction When the port latch of an I/O port is modified with the bit managing instruction* 2, the value of the unspecified bit may be changed. q Reason The bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an I/O port, the following is executed to all bits of the port latch. * As for a bit which is set for an input port : The pin state is read in the CPU, and is written to this bit after bit managing. * As for a bit which is set for an output port : The bit value of the port latch is read in the CPU, and is written to this bit after bit managing. Note the following : * Even when a port which is set as an output port is changed for an input port, its port latch holds the output data. * As for a bit of the port latch which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents. * 2 bit managing instructions : SEB, and CLB instructions (3) Usage for the 32-pin version Fix the P35, P36 pull-up control bit of the pull-up control register to "1". Keep the P36/INT1 input level selection bit of the port P1P3 control register "0" (initial state). Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-73 APPENDIX 7540 Group 3.3 Notes on use 3.3.2 Termination of unused pins (1) Terminate unused pins I/O ports : * Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of 1 k to 10 k. Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the I/ O ports for the output mode and open them at "L" or "H". * When opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side. * Since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. (2) Termination remarks Input ports and I/O ports : Do not open in the input mode. q Reason * The power source current may increase depending on the first-stage circuit. * An effect due to noise may be easily produced as compared with proper termination and shown on the above. I/O ports : When setting for the input mode, do not connect to VCC or VSS directly. q Reason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and VCC (or VSS). I/O ports : When setting for the input mode, do not connect multiple ports in a lump to VCC or VSS through a resistor. q Reason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. * At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-74 APPENDIX 7540 Group 3.3 Notes on use 3.3.3 Notes on Timer * When n (0 to 255) is written to a timer latch, the frequency division ratio is 1/(n+1). * When a count source of timer X, timer Y or timer Z is switched, stop a count of timer X. 3.3.4 Notes on Timer A Notes on using timer A are described below. (1) Common to all modes When reading timer A (high-order) (TAH) and timer A (low-order) (TAL), the contents of timer A is read out. Read both registers in order of TAH and TAL following, certainly. TAH and TAL keep the values until they are read out. Also, do not write to them during read. In this case, unexpected operation may occur. When writing data to TAL and TAH even when timer A is operating or stopped, the data are set to timer A and timer A latch simultaneously. Write both registers in order of TAL and TAH following, certainly. Also, do not read them during write. In this case, unexpected operation may occur. (2) Period measurement mode, event counter mode, and pulse width HL continuously measurement mode In order to use CNTR1 pin, set "0" to bit 0 of the port P0 direction register (input mode). In order to use CNTR1 pin, set "1" to bit 7 of the interrupt control register to disable the P00 keyon wakeup function. CNTR1 interrupt active edge depends on the CNTR1 active edge switch bit. When this bit is "0", the CNTR1 interrupt request bit is set to "1" at the falling edge of the CNTR1 pin input signal. When this bit is "1", the CNTR1 interrupt request bit is set to "1" at the rising edge of the CNTR1 pin input signal. However, in the pulse width HL continuously measurement mode, CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR1 active edge switch bit. 3.3.5 Notes on timer 1 Note on timer 1 is described below. (1) Notes on set of the oscillation stabilizing time Timer 1 can be used to set the oscillation stabilizing time after release of the STP instruction. The oscillation stabilizing time after release of STP instruction can be selected from "set automatically"/ "not set automatically" by the oscillation stabilizing time set bit after release of the STP instruction of MISRG. When "0" is set to this bit, "0116" is set to timer 1 and "FF16" is set to prescaler 1 automatically. When "1" is set to this bit, nothing is set to timer 1 and prescaler 1. Therefore, set the wait time according to the oscillation stabilizing time of the oscillation. Also, when timer 1 is used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-75 APPENDIX 7540 Group 3.3 Notes on use 3.3.6 Notes on Timer X Notes on using each mode of timer X are described below. (1) Count source f(XIN) can be used only when a ceramic oscillator or an on-chip oscillator is used. Do not use f(XIN) at RC oscillation. (2) Pulse output mode In order to use CNTR0 pin, set "1" to bit 4 of the port P1 direction register (output mode). In order to use TXOUT pin, set "1" to bit 3 of the port P0 direction register (output mode). CNTR0 interrupt active edge depends on the CNTR0 active edge switch bit. When this bit is "0", the CNTR0 interrupt request bit is set to "1" at the falling edge of CNTR0 pin input signal. When this bit is "1", the CNTR0 interrupt request bit is set to "1" at the rising edge of CNTR0 pin input signal. (3) Pulse width measurement mode In order to use CNTR0 pin, set "1" to bit 4 of the port P1 direction register (output mode). CNTR0 interrupt active edge depends on the CNTR0 active edge switch bit. When this bit is "0", the CNTR0 interrupt request bit is set to "1" at the falling edge of CNTR0 pin input signal. When this bit is "1", the CNTR0 interrupt request bit is set to "1" at the rising edge of CNTR0 pin input signal. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-76 APPENDIX 7540 Group 3.3 Notes on use 3.3.7 Notes on timer Y and timer Z Notes on using each mode of Timer Y and Timer Z are described below. (1) Timer mode (timer Y and timer Z) In the timer mode, TYP and TYS is not used. (2) Programmable waveform generation mode (timer Y and timer Z) In the programmable waveform generation mode, values of TYS, EXPYP, and EXPYS are valid by writing to TYP because the setting to them is executed all at once by writing to TYP. Even when changing TYP is not required, write the same value again. In the programmable waveform generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TYP and the timing of timer underflow during the secondary interval simultaneously. An example of a measurement is shown below. ex.) The underflow by the primary and the underflow by secondary are stored by polling etc. using timer Y interrupt. Writing to primary is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (Depending on a primary and a secondary setting values, and primary write timing, it may be impossible.) The waveform extension function by the timer Y waveform extension control bits can be used only when "0016" is set to Prescaler Y. When the value other than "0016" is set to Prescaler Y, be sure to set "0" to EXPYP and EXPYS. The waveform extension function by the timer Z waveform extension control bits can be used only when "0016" is set to Prescaler Z. When the value other than "0016" is set to Prescaler Z, be sure to set "0" to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used. When using this mode, be sure to set "1" to the timer Y write control bit to select "write to latch only". When TYS is read out, the undefined value is read out. However, while timer Y counts the setting value of TYS, the count value during the secondary interval can be obtained by reading the timer Y primary. In order to use TYOUT pin, set "1" to bit 1 of the port P0 direction register (output mode). (3) Programmable one-shot generation mode (timer Z) In the programmable one-shot generation mode, the value of EXPZP becomes valid by writing to TZP. Even when changing TZP is not required, write the same value again. In the programmable one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow simultaneously. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-77 APPENDIX 7540 Group 3.3 Notes on use The waveform extension function by the timer Z waveform extension control bits can be used only when "0016" is set to Prescaler Z. When the value other than "0016" is set to Prescaler Z, be sure to set "0" to EXPZP. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used. An example of a measurement is shown below. ex.) The underflow of timer is stored by polling etc. using timer Z interrupt. Writing to primary is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (Depending on a primary setting value, primary write timing, software and timing of external trigger to INT0 pin, it may be impossible.) When using this mode, be sure to set "1" to the timer Z write control bit to select "write to latch only". In order to use TZOUT pin, set "1" to bit 2 of the port P0 direction register (output mode). Stop Timer Z to change the INT0 pin one-shot trigger control bit and INT0 pin one-shot trigger active edge selection bit. (4) Programmable wait one-shot generation mode (timer Z) In the programmable wait one-shot generation mode, values of TZS, EXPZP and EXPZS are valid by writing to TZP. Even when changing TZP is not required, write the same value again. An example of a measurement is shown below. ex.) The underflow by the primary and the underflow by secondary are stored by polling etc. using timer Z interrupt. Writing is performed in by judging that there is no problem if the underflow by secondary is completed with reference to primary write operation before. (Depending on a primary setting value, primary write timing, software and timing of external trigger to INT0 pin, it may be impossible.) In the programmable wait one-shot generation mode, when the setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of timer underflow during the secondary interval simultaneously. The waveform extension function by the timer Z waveform extension control bit can be used only when "0016" is set to Prescaler Z. When the value other than "0016" is set to Prescaler Z, be sure to set "0" to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension function cannot be used. When using this mode, be sure to set "1" to the timer Z write control bits to select "write to latch only". When TZS is read out, the undefined value is read out. However, while Timer Z counts the setting value of TZS (during one-shot output), the count value during the secondary interval can be obtained by reading TZP. In order to use TZOUT pin, set "1" to bit 2 of the port P0 direction register (output mode). Stop Timer Z to change the INT0 pin one-shot trigger control bit and INT0 pin one-shot trigger active edge selection bit. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-78 APPENDIX 7540 Group 3.3 Notes on use (5) Common to all modes (timer Y and timer Z) Timer Y can stop counting by setting "1" to the timer Y count stop bit in any mode. Also, when Timer Y underflows, the timer Y interrupt request bit is set to "1". Timer Y reloads the value of latch when counting is stopped by the timer Y count stop bit. (When timer is read out while timer is stopped, the value of latch is read. The value of timer can be read out only while timer is operating.) 3.3.8 Notes on Serial I/O1 Notes on using serial I/O1 are described below. (1) Notes when selecting clock synchronous serial I/O When the clock synchronous serial I/O1 is used, serial I/O2 cannot be used. When the transmit operation is stopped, clear the serial I/O1 enable bit and the transmit enable bit to "0" (serial I/O1 and transmit disabled). q Reason Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to "0" (serial I/O1 disabled), the internal transmission is running (in this case, since pins TxD1, RxD1, SCLK1, and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to "1" at this time, the data during internally shifting is output to the TxD1 pin and an operation failure occurs. When the receive operation is stopped, clear the receive enable bit to "0" (receive disabled), or clear the serial I/O1 enable bit to "0" (serial I/O1 disabled). When the transmit/receive operation is stopped, clear both the transmit enable bit and receive enable bit to "0" (transmit and receive disabled) simultaneously. (any one of data transmission and reception cannot be stopped.) q Reason In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to "0" (transmit disabled). Also, the transmission circuit cannot be initialized even if the serial I/O1 enable bit is cleared to "0" (serial I/O1 disabled) (same as ). When signals are output from the SRDY1 pin on the reception side by using an external clock, set all of the receive enable bit, the SRDY1 output enable bit, and the transmit enable bit to "1". When the SRDY1 signal input is used, set the using pin to the input mode before data is written to the transmit/receive buffer register. Setup of a serial I/O1 synchronous clock selection bit when a clock synchronous serial I/O is selected; "0" : P12 pin turns into an output pin of a synchronous clock. "1" : P12 pin turns into an input pin of a synchronous clock. Setup of a SRDY1 output enable bit (SRDY1) when a clock synchronous serial I/O1 is selected; "0" : P13 pin can be used as a normal I/O pin. "1" : P13 pin turns into a SRDY1 output pin. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-79 APPENDIX 7540 Group 3.3 Notes on use (2) Notes when selecting UART When the clock asynchronous serial I/O1 (UART) is used, serial I/O2 can be used only when BRG output divided by 16 is selected as the synchronous clock. When the transmit operation is stopped, clear the transmit enable bit to "0" (transmit disabled). q Reason Same as (1) . When the receive operation is stopped, clear the receive enable bit to "0" (receive disabled). When the transmit/receive operation is stopped, clear the transmit enable bit to "0" (transmit disabled) and receive enable bit to "0" (receive disabled). Setup of a serial I/O1 synchronous clock selection bit when a clock asynchronous (UART) serial I/O is selected; "0": P12 pin can be used as a normal I/O pin. "1": P12 pin turns into an input pin of an external clock. When clock asynchronous (UART) type serial I/O is selected, it is P13 pin. It can be used as a normal I/O pin. (3) Notes common to clock synchronous serial I/O and UART Set the serial I/O control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to "0." The transmit shift completion flag changes from "1" to "0" with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. Clear both the transmit enable bit (TE) and the receive enable bit (RE) to "0" Set the bits 0 to 3 and bit 6 of the serial I/O1 control register Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to "1" Fig. 3.3.1 Sequence of setting serial I/O1 control register again When data transmission is executed at the state that an external clock input is selected as the synchronous clock, set "1" to the transmit enable bit while the SCLK1 is "H" state. Also, write to the transmit buffer register while the SCLK1 is "H" state. When the transmit interrupt is used, set as the following sequence. Serial I/O1 transmit interrupt enable bit is set to "0" (disabled). Serial I/O1 transmit enable bit is set to "1". Serial I/O1 transmit interrupt request bit is set to "0". Serial I/O1 transmit interrupt enable bit is set to "1" (enabled). q Reason When the transmit enable bit is set to "1", the transmit buffer empty flag and transmit shift completion flag are set to "1". Accordingly, even if the timing when any of the above flags is set to "1" is selected for the transmit interrupt source, interrupt request occurs and the transmit interrupt request bit is set. Write to the baud rate generator (BRG) while the transmit/receive operation is stopped. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z Can be set with the LDM instruction at the same time 3-80 APPENDIX 7540 Group 3.3 Notes on use 3.3.9 Notes on serial I/O2 Notes on using serial I/O2 are described below. (1) Note on serial I/O1 Serial I/O2 can be used only when serial I/O1 is not used or serial I/O1 is used as UART and the BRG output divided by 16 is selected as the synchronous clock. (2) Note on SCLK2 pin When an external clock is selected, set "0" to bit 2 of the port P1 direction register (input mode). (3) Note on SDATA2 pin When P13/SRDY1/SDATA2 pin is used as the SDATA input, set "0" to bit 3 of the port P1 direction register (input mode). When the internal clock is selected as the transfer and P13/SDATA2 pin is set to the input mode, the SDATA2 pin is in a high-impedance state after the data transfer is completed. (4) Notes on serial I/O2 transmit/receive shift completion flag The transmit/receive shift completion flag of the serial I/O2 control register is "1" after transmit/ receive shift is completed. In order to set "0" to this flag, set data (dummy data at receive) to the serial I/O2 register by program. Bit 7 (transmit/receive shift completion flag) of the serial I/O2 control register is set earlier than the completion of the actual shift operation for a half cycle of shift clock. Accordingly, when the shift completion is checked by using this bit, read/write the serial I/O2 register after a half or more cycle of clock from the setting "1" to this bit is checked. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-81 APPENDIX 7540 Group 3.3 Notes on use 3.3.10 Notes on A/D converter Notes on A/D converter are described below. (1) Analog input pin Figure 3.3.2 shows the internal equivalent circuit of an analog input. In order to execute the A/D conversion correctly, to complete the charge to an internal capacitor within the specified time is required. The maximum output impedance of the analog input source required to complete the charge to a capacitor within the specified time is as follows; About 35 k (at f(XIN) = 8 MHz) When the maximum output impedance exceeds the above value, equip an analog input pin with an external capacitor of 0.01F to 1F between an analog input pin and VSS. Further, be sure to verify the operation of application products on the user side. q Reason An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when signals from signal source with high impedance are input to an analog input pin, charge and discharge noise generates. This may cause the A/D conversion/comparison precision to be worse. VCC (Note 1) R 1.5 k(Typical) ANi (i=0 to 7: 36-pin version i=0 to 5: 32-pin version) C2 1.5 pF(Typical) SW1 (Note 2) (Note 1) Typical voltage generation circuit Switch tree, ladder resistor Chopper Amp. C1 12 pF(Typical) VSS VSS Notes 1: This is a parasitic diode. 2: Only the selected analog input pin is turned on. A/D control circuit VSS VREF Fig. 3.3.2 Connection diagram (2) Clock frequency during A/D conversion The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is too low. Thus, make sure the following during an A/D conversion. * f(XIN) is 500 kHz or more * Do not execute the STP instruction (3) Note on A/D converter As for AD translation accuracy, on the following operating conditions, accuracy may become low. (1) Since the analog circuit inside a microcomputer becomes sensitive to noise when VREF voltage is set up lower than Vcc voltage, accuracy may become low rather than the case where VREF voltage and Vcc voltage are set up to the same value. (2) When VREF voltage is lower than [3.0 V], the accuracy at the low temperature may become extremely low compared with that at room temperature When the system would be used at low temperature, the use at VREF=3.0 V or more is recommended. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-82 APPENDIX 7540 Group 3.3 Notes on use 3.3.11 Notes on oscillation stop detection circuit Notes on using oscillation stop detection circuit are described below. (1) Note on on-chip oscillator The 7540 Group starts operation by the on-chip oscillator. On-chip oscillator operation The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. (2) Notes on oscillation circuit stop detection circuit When the stop mode is used, set the oscillation stop detection function to "invalid". When f(XIN) oscillation is stopped, set the oscillation stop detection function to "invalid". The oscillation stop detection circuit is not included in the emulator MCU "M37540RSS". (3) Notes on stop mode When the stop mode is used, set the oscillation stop detection function to "invalid". When the stop mode is used, set "0" (STP instruction enabled) to the STP instruction disable bit of the watchdog timer control register. Timer 1 can be used to set the oscillation stabilizing time after release of the STP instruction. The oscillation stabilizing time after release of STP instruction can be selected from "set automatically"/ "not set automatically" by the oscillation stabilizing time set bit after release of the STP instruction of MISRG. When "0" is set to this bit, "0116" is set to timer 1 and "FF16" is set to prescaler 1 automatically. When "1" is set to this bit, nothing is set to timer 1 and prescaler 1. Therefore, set the wait time according to the oscillation stabilizing time of the oscillation. Also, when timer 1 is used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode. The STP instruction cannot be used during CPU is operating by the on-chip oscillator. When the stop mode is used, stop the on-chip oscillator oscillation. Do not execute the STP instruction during the A/D conversion. (4) Note on wait mode When the wait mode is used, stop the clock except the operation clock source. (5) Notes on state transition When the operation clock source is f(XIN), the CPU clock division ratio can be selected from the following; * f(XIN)/2 (high-speed mode) * f(XIN)/8 (middle-speed mode) * f(XIN) (double-speed mode) The double-speed mode can be used only at ceramic oscillation. Do not use the mode at RC oscillation. Stabilize the f(XIN) oscillation to change the operation clock source from the on-chip oscillator to f(XIN). Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-83 APPENDIX 7540 Group 3.3 Notes on use When the on-chip oscillation is used as the operation clock, the CPU clock division ratio is the middle-speed mode. When the state transition state 2state 3state 4 is performed, execute the NOP instruction as shown below according to the division ratio of CPU clock. * CPUM76102 (State 2state 3) * NOP instruction * CPUM412 (State 3state 4) Double-speed mode at on-chip oscillator: NOP3 High-speed mode at on-chip oscillator: NOP1 Middle-speed mode at on-chip oscillator: NOP0 (6) Switch of ceramic and RC oscillations After releasing reset the operation starts by starting an on-chip oscillator. Then, a ceramic oscillation or an RC oscillation is selected by setting bit 5 of the CPU mode register. (7) Double-speed mode When a ceramic oscillation is selected, a double-speed mode can be used. Do not use it when an RC oscillation is selected. (8) Clock division ratio, XIN oscillation control, on-chip oscillator control The state transition shown in Figure 3.3.3 can be performed by setting the clock division ratio selection bits (bits 7 and 6), XIN oscillation control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of CPU mode register. Be careful of notes on use in Figure 3.3.3. Stop mode Interrupt Interrupt STP instruction Wait mode WIT instruction Interrupt WIT instruction State 3 Operation clock source: On-chip oscillator (Note 3) f(XIN) oscillation enabled On-chip oscillator enalbed CPUM412 State 1 Operation clock source: f(XIN) (Note 1) f(XIN) oscillation enabled On-chip oscillator stop CPUM302 CPUM312 State 2 CPUM76102 Operation clock source: f(XIN) (Note 1) f(XIN) oscillation enabled On-chip oscillator enabled CPUM76002 012 112 (Note 2) CPUM402 State 4 Operation clock source: On-chip oscillator (Note 3) f(XIN) oscillation stop On-chip oscillator enalbed MISRG112 MISRG102 MISRG112 MISRG102 State 2' CPUM76102 Operation clock source: f(XIN) (Note 1) f(XIN) oscillation enabled On-chip oscillator enabled CPUM76002 012 112 (Note 2) State 3' Operation clock source: On-chip oscillator (Note 3) f(XIN) oscillation enabled On-chip oscillator enalbed Oscillation stop detection circuit valid Reset released Reset state Notes on switch of clock (1) In operation clock source = f(XIN), the following can be selected for the CPU clock division ratio. q f(XIN)/2 (high-speed mode) q f(XIN)/8 (middle-speed mode) q f(XIN) (double-speed mode, only at a ceramic oscillation) (2) Execute the state transition state 3 to state 2 or state 3' to state 2' after stabilizing XIN oscillation. (3) In operation clock source = on-chip oscillator, the middlespeed mode is selected for the CPU clock division ratio. (4) When the state transition state 2 state 3 state 4 is performed, execute the NOP instruction as shown below according to the division ratio of CPU clock. * CPUM76 102 (State 2 state 3) * NOP instruction * CPUM4 12 (State 3 state 4) Double-speed mode at on-chip oscillator: NOP 3 High-speed mode at on-chip oscillator: NOP 1 Middle-speed mode at on-chip oscillator: NOP 0 Fig. 3.3.3 State transition Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-84 APPENDIX 7540 Group 3.3 Notes on use 3.3.12 Notes on CPU mode register (1) Switching method of CPU mode register after releasing reset Switch the CPU mode register (CPUM) at the head of program after releasing reset in the following method. After releasing reset Start with an on-chip oscillator (Note) Switch the oscillation mode selection bit (bit 5 of CPUM) An initial value is set as a ceramic oscillation mode. When it is switched to an RC oscillation, its oscillation starts. Wait by on-chip oscillator operation until establishment of oscillator clock When using a ceramic oscillation, wait until establlishment of oscillation from oscillation starts. When using an RC oscillation, wait time is not required basically (time to execute the instruction to switch from an on-chip oscillator meets the requirement). Select 1/1, 1/2, 1/8 or on-chip oscillator. Switch the clock division ratio selection bits (bits 6 and 7 of CPUM) Main routine Note. After releasing reset the operation starts by starting an on-chip oscillator automatically. Do not use an on-chip oscillator at ordinary operation. Fig. 3.3.4 Switching method of CPU mode register (2) CPU mode register Bits 5, 1 and 0 of CPU mode register are used to select oscillation mode and to control operation modes of the microcomputer. In order to prevent the dead-lock by error-writing (ex. program runaway), these bits can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. (The emulator MCU "M37540RSS" is excluded.) Also, when the read-modify-write instructions (SEB, CLB) are executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-85 APPENDIX 7540 Group 3.3 Notes on use 3.3.13 Notes on interrupts (1) Switching external interrupt detection edge For the products able to switch the external interrupt detection edge, switch it as the following sequence. Clear an interrupt enable bit to "0" (interrupt disabled) Switch the detection edge NOP (one or more instructions) Clear an interrupt request bit to "0" (no interrupt request issued) Set the interrupt enable bit to "1" (interrupt enabled) Fig. 3.3.5 Sequence of switch the detection edge q Reason The interrupt circuit recognizes the switching of the detection edge as the change of external input signals. This may cause an unnecessary interrupt. (2) Check of interrupt request bit When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request register immediately after this bit is set to "0" by using a data transfer instruction, execute one or more instructions before executing the BBC or BBS instruction. q Reason If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt request register is cleared to "0", the value of the interrupt request bit before being cleared to "0" is read. Clear the interrupt request bit to "0" (no interrupt issued) NOP (one or more instructions) Execute the BBC or BBS instruction Data transfer instruction: LDM, LDA, STA, STX, and STY instructions Fig. 3.3.6 Sequence of check of interrupt request bit Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-86 APPENDIX 7540 Group 3.3 Notes on use (3) Structure of interrupt control register 2 Fix the bit 7 of the interrupt control register 1 to "0". Figure 3.3.7 shows the structure of the interrupt control register 2. b7 b0 Interrupt control register 2 (address: 003F16) Interrupt enable bit Not used (fix this bit to "0") 0 Fig. 3.3.7 Structure of interrupt control register 2 (4) Interrupt When setting the followings, the interrupt request bit may be set to "1". *When switching external interrupt active edge Related register: Interrupt edge selection register (address 003A16) Timer X mode register (address 002B16) Timer A mode register (address 001D16) When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. Set the corresponding interrupt enable bit to "0" (disabled). Set the interrupt edge select bit (active edge switch bit). Set the corresponding interrupt request bit to "0" after 1 or more instructions have been executed. Set the corresponding interrupt enable bit to "1" (enabled). 3.3.14 Notes on RESET pin (1) Connecting capacitor In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the RESET pin and the VSS pin. And use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, note the following : * Make the length of the wiring which is connected to a capacitor as short as possible. * Be sure to verify the operation of application products on the user side. q Reason If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may cause a microcomputer failure. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-87 APPENDIX 7540 Group 3.3 Notes on use 3.3.15 Notes on programming (1) Processor status register Initializing of processor status register Flags which affect program execution must be initialized after a reset. In particular, it is essential to initialize the T and D flags because they have an important effect on calculations. q Reason After a reset, the contents of the processor status register (PS) are undefined except for the I flag which is "1". Reset Initializing of flags Main program Fig. 3.3.8 Initialization of processor status register How to reference the processor status register To reference the contents of the processor status register (PS), execute the PHP instruction once then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its original status. A NOP instruction should be executed after every PLP instruction. PLP instruction execution NOP (S) (S)+1 Stored PS Fig. 3.3.9 Sequence of PLP instruction execution Fig. 3.3.10 Stack memory contents after PHP instruction execution Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-88 APPENDIX 7540 Group 3.3 Notes on use (2) Decimal calculations Execution of decimal calculations The ADC and SBC are the only instructions which will yield proper decimal notation, set the decimal mode flag (D) to "1" with the SED instruction. After executing the ADC or SBC instruction, execute another instruction before executing the SEC, CLC, or CLD instruction. Notes on status flag in decimal mode When decimal mode is selected, the values of three of the flags in the status register (the N, V, and Z flags) are invalid after a ADC or SBC instruction is executed. The carry flag (C) is set to "1" if a carry is generated as a result of the calculation, or is cleared to "0" if a borrow is generated. To determine whether a calculation has generated a carry, the C flag must be initialized to "0" before each calculation. To check for a borrow, the C flag must be initialized to "1" before each calculation. Set D flag to "1" ADC or SBC instruction NOP instruction SEC, CLC, or CLD instruction Fig. 3.3.11 Status flag at decimal calculations (3) JMP instruction When using the JMP instruction in indirect addressing mode, do not specify the last address on a page as an indirect address. (4) Interrupts The contents of the interrupt request bit do not change even if the BBC or BBS instruction is executed immediately after they are changed by program because this instruction is executed for the previous contents. For executing the instruction for the changed contents, execute one instruction before executing the BBC or BBS instruction. (5) Ports * The values of the port direction registers cannot be read. That is, it is impossible to use the LDA instruction, memory operation instruction when the T flag is "1", addressing mode using direction register values as qualifiers, and bit test instructions such as BBC and BBS. It is also impossible to use bit operation instructions such as CLB and SEB and read/modify/write instructions of direction registers for calculations such as ROR. For setting direction registers, use the LDM instruction, STA instruction, etc. (6) A/D Conversion Do not execute the STP instruction during A/D conversion. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-89 APPENDIX 7540 Group 3.3 Notes on use (7) Instruction Execution Timing The instruction execution time can be obtained by multiplying the frequency of the internal clock f by the number of cycles mentioned in the machine-language instruction table. The frequency of the internal clock f is the same as that of the XIN in double-speed mode, twice the XIN cycle in high-speed mode and 8 times the XIN cycle in middle-speed mode. (8) CPU Mode Register The oscillation mode selection bit and processor mode bits can be rewritten only once after releasing reset. However, after rewriting it is disable to write any value to the bit. (Emulator MCU is excluded.) When a ceramic oscillation is selected, a double-speed mode of the clock division ratio selection bits can be used. Do not use it when an RC oscillation is selected. 3.3.16 Programming and test of built-in PROM version As for in the One Time PROM version (shipped in blank), its built-in PROM can be read or programmed with a general-purpose PROM programmer using a special programming adapter. The programming test and screening for PROM of the One Time PROM version (shipped in blank) are not performed in the assembly process and the following processes. To ensure reliability after programming, performing programming and test according to the Figure 3.3.12 before actual use are recommended. Programming with PROM programmer Screening (Caution) (150 C for 40 hours) Verification with PROM programmer Functional check in target device Caution: The screening temperature is far higher than the storage temperature. Never expose to 150 C exceeding 100 hours. Fig. 3.3.12 Programming and testing of One Time PROM version (1) One Time PROM Version The CNVss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (VPP pin) as well. To improve the noise reduction, connect a track between CNVss pin and Vss pin with 1 to 10 k resistance. The mask ROM version track of CNVss pin has no operational interference even if it is connected via a resistor. 3.3.17 Handling of Power Source Pin In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 F to 0.1 F is recommended. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-90 APPENDIX 7540 Group 3.3 Notes on use 3.3.18 Notes on built-in PROM version (1) Programming adapter Use a special programming adapter shown in Table 3.3.1 and a general-purpose PROM programmer when reading from or programming to the built-in PROM in the built-in PROM version. Table 3.3.1 Programming adapters Part Number M37540E8GP (One Time PROM version shipped in blank) M37540E8SP (One Time PROM version shipped in blank) M37540E8FP (One Time PROM version shipped in blank) Programming adapter PCA7435GPG03 PCA7435SPG02 PCA7435FPG02 (2) Programming/reading In PROM mode, operation is the same as that of the M5M27C101AK, but programming conditions of PROM programmer are not set automatically because there are no internal device ID codes. Accurately set the following conditions for data programming /reading. Take care not to apply 21 V to VPP pin (is also used as the CNVSS pin), or the product may be permanently damaged. * Programming voltage: 12.5 V * Setting of PROM programmer switch: refer to Table 3.3.2. Table 3.3.2 PROM programmer address setting PROM programmer Part Number start address M37540E8GP M37540E8SP M37540E8FP Note: Addersses 808016 to FFFD16 in the built-in PROM corresponds to addresses 0808016 to 0FFFD16 in the PROM programmer. Address 0808016 (Note) Address 0FFFD16 (Note) PROM programmer end address 3.3.19 Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. 3.3.20 Electric Characteristic Differences Among Mask ROM and One TIme PROM Version MCUs There are differences in electric characteristics, operation margin, noise immunity, and noise radiation among mask ROM and One Time PROM version MCUs due to the differences in the manufacturing processes. When manufacturing an application system with One Time PROM version and then switching to use of the mask ROM version, perform sufficient evaluations for the commercial samples of the mask ROM version. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-91 APPENDIX 7540 Group 3.4 Countermeasures against noise 3.4 Countermeasures against noise 3.4.1 Shortest wiring length (1) Package Select the smallest possible package to make the total wiring length short. q Reason The wiring length depends on a microcomputer package. Use of a small package, for example QFP and not DIP, makes the total wiring length short to reduce influence of noise. DIP SDIP SOP QFP Fig. 3.4.1 Selection of packages (2) Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within 20mm). q Reason The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Noise Reset circuit VSS N.G. RESET VSS Reset circuit VSS RESET VSS O.K. Fig. 3.4.2 Wiring for the RESET pin Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-92 APPENDIX 7540 Group 3.4 Countermeasures against noise (3) Wiring for clock input/output pins * Make the length of wiring which is connected to clock I/O pins as short as possible. * Make the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. * Separate the VSS pattern only for oscillation from other VSS patterns. q Reason If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer. Noise XIN XOUT VSS N.G. XIN XOUT VSS O.K. Fig. 3.4.3 Wiring for clock I/O pins (4) Wiring to CNVSS pin Connect the CNVSS pin to the VSS pin with the shortest possible wiring. q Reason The processor mode of a microcomputer is influenced by a potential at the CNVSS pin. If a potential difference is caused by the noise between pins CNVSS and VSS, the processor mode may become unstable. This may cause a microcomputer malfunction or a program runaway. Noise CNVSS VSS CNVSS VSS N.G. O.K. Fig. 3.4.4 Wiring for CNVSS pin Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-93 APPENDIX 7540 Group 3.4 Countermeasures against noise (5) Wiring to VPP pin of One Time PROM version Connect an approximately 5 k resistor to the VPP pin the shortest possible in series and also to the VSS pin. When not connecting the resistor, make the length of wiring between the VPP pin and the VSS pin the shortest possible. Note: Even when a circuit which included an approximately 5 k resistor is used in the Mask ROM version, the microcomputer operates correctly. q Reason The VPP pin of the One Time PROM is the power source input pin for the built-in PROM. When programming in the built-in PROM, the impedance of the VPP pin is low to allow the electric current for writing flow into the PROM. Because of this, noise can enter easily. If noise enters the VPP pin, abnormal instruction codes or data are read from the built-in PROM, which may cause a program runaway. Approximately 5k CNVSS/VPP VSS In the shortest distance Fig. 3.4.5 Wiring for the VPP pin of the One Time PROM 3.4.2 Connection of bypass capacitor across VSS line and VCC line Connect an approximately 0.1 F bypass capacitor across the VSS line and the VCC line as follows: * Connect a bypass capacitor across the VSS pin and the VCC pin at equal length. * Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring. * Use lines with a larger diameter than other signal lines for VSS line and VCC line. * Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin. VCC VCC VSS VSS N.G. O.K. Fig. 3.4.6 Bypass capacitor across the VSS line and the VCC line Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-94 APPENDIX 7540 Group 3.4 Countermeasures against noise 3.4.3 Wiring to analog input pins * Connect an approximately 100 to 1 k resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible. * Connect an approximately 1000 pF capacitor across the VSS pin and the analog input pin. Besides, connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog input pin and the VSS pin at equal length. q Reason Signals which is input in an analog input pin (such as an A/D converter/comparator input pin) are usually output signals from sensor. The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin. Noise (Note) Microcomputer Analog input pin N.G. O.K. Thermistor VSS Note : The resistor is used for dividing resistance with a thermistor. Fig. 3.4.7 Analog signal line and a resistor and a capacitor 3.4.4 Oscillator concerns Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. q Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. Microcomputer Mutual inductance M Large current GND XIN XOUT VSS Fig. 3.4.8 Wiring for a large current signal line Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-95 APPENDIX 7540 Group 3.4 Countermeasures against noise (2) Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. q Reason Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. 3) Oscillator protection using VSS pattern As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. Connect the VSS pattern to the microcomputer VSS pin with the shortest possible wiring. Besides, separate this VSS pattern from other VSS patterns. An example of VSS patterns on the underside of a printed circuit board N.G. Do not cross CNTR XIN XOUT VSS Oscillator wiring pattern example XIN XOUT VSS Fig. 3.4.9 Wiring of signal lines where potential levels change frequently Separate the VSS line for oscillation from other VSS lines Fig. 3.4.10 VSS pattern on the underside of an oscillator 3.4.5 Setup for I/O ports Setup I/O ports using hardware and software as follows: O.K. Noise Data bus Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z Direction register N.G. Port latch I/O port pins Noise Fig. 3.4.11 Setup for I/O ports 3-96 APPENDIX 7540 Group 3.4 Countermeasures against noise 3.4.6 Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing. Main routine (SWDT) N CLI Main processing N (SWDT) =N? N Interrupt processing routine (SWDT) (SWDT)--1 Interrupt processing (SWDT) 0? 0 >0 RTI Return Main routine errors Interrupt processing routine errors Fig. 3.4.12 Watchdog timer by software Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-97 APPENDIX 7540 Group 3.5 List of registers 3.5 List of registers Port Pi b7 b6 b5 b4 b3 b2 b1 b0 Port Pi (Pi) (i = 0, 2, 3) [Address : 00 16, 0416, 0616] B 0 Port Pi0 1 Port Pi1 Name q Function In output mode Write Port latch Read In input mode Write : Port latch Read : Value of pins At reset RW ? ? ? ? ? ? ? ? q 2 Port Pi2 3 Port Pi3 4 Port Pi4 5 Port Pi5 6 Port Pi6 7 Port Pi7 Note: The 32-pin package versions have nothing to be allocated for the following: *Bits 6 and 7 of port P2 *Bits 5 and 6 of port P3. Fig. 3.5.1 Structure of Port Pi (i = 0, 2, 3) Port P1 b7 b6 b5 b4 b3 b2 b1 b0 Port P1 (P1) [Address : 02 16] B 0 Port P10 1 Port P11 Name q Function In output mode Write Port latch Read In input mode Write : Port latch Read : Value of pins At reset RW ? ? ? ? ? ? ? ? q 2 Port P12 3 Port P13 4 Port P14 5 Nothing is allocated for these bits. When these bits are read out, the values are undefined. 6 7 Fig. 3.5.2 Structure of Port P1 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-98 APPENDIX 7540 Group 3.5 List of registers Port Pi direction register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (PiD) (i = 0, 2, 3) [Address : 01 16, 0516, 0716] At reset B Name Function 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode RW 0 Port Pi direction register 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 Note: The 32-pin package versions have nothing to be allocated for the following: *Bits 6 and 7 of P2D *Bits 5 and 6 of P3D. Fig. 3.5.3 Structure of Port Pi direction register (i = 0, 2, 3) Port P1 direction register b7 b6 b5 b4 b3 b2 b1 b0 Port P1 direction register (P1D) [Address : 03 16] B Name Function 0 : Port P10 input mode 1 : Port P10 output mode 0 : Port P11 input mode 1 : Port P11 output mode 0 : Port P12 input mode 1 : Port P12 output mode 0 : Port P13 input mode 1 : Port P13 output mode 0 : Port P14 input mode 1 : Port P14 output mode At reset RW 0 Port P1 direction register 1 2 3 4 0 0 0 0 0 ? ? ? 5 Nothing is allocated for these bits. When these bits are read out, the values are undefined. 6 7 Fig. 3.5.4 Structure of Port P1 direction register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-99 APPENDIX 7540 Group 3.5 List of registers Pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 Pull-up control register (PULL) [Address : 1616] Name B P00 pull-up control bit 0 1 P01 pull-up control bit 2 P02, P03 pull-up control bit 3 P04 - P07 pull-up control bit 4 P30 - P33 pull-up control bit 5 P34 pull-up control bit 6 P35, P36 pull-up control bit 7 P37 pull-up control bit Function 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On 0 : Pull-up Off 1 : Pull-up On At reset RW 0 0 0 0 0 0 0 0 Note: Pins set to output are disconnected from the pull-up control. Fig. 3.5.5 Structure of Pull-up control register Port P1P3 control register b7 b6 b5 b4 b3 b2 b1 b0 Port P1P3 control register (P1P3C) [Address : 17 16] B bit Name Function 0 : CMOS level 1 : TTL level 0 : CMOS level 1 : TTL level 0 : CMOS level 1 : TTL level At reset RW 0 P37/INT0 input level selection 1 P36/INT1 input level selection bit (Note) 2 P10, P12,P13 input level selection bit 0 0 0 0 0 0 0 0 3 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 4 5 6 7 Note: Keep setting the P3 6/INT1 input level selection bit to "0" (initial value) for the 32-pin package version. Fig. 3.5.6 Structure of Port P1P3 control register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-100 APPENDIX 7540 Group 3.5 List of registers Transmit/Receive buffer register b7 b6 b5 b4 b3 b2 b1 b0 Transmit/Receive buffer register (TB/RB) [Address : 18 16] B Function At reset RW 0 The transmission data is written to or the receive data is read out from this buffer register. 1 * At writing: A data is written to the transmit buffer register. * At reading: The contents of the receive buffer register are read out. 2 ? ? ? ? ? ? ? ? 3 4 5 6 7 Note: The contents of transmit buffer register cannot be read out. The data cannot be written to the receive buffer register. Fig. 3.5.7 Structure of Transmit/Receive buffer register Serial I/O1 status register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O1 status register (SIO1STS) [Address : 19 16] B (TBE) Name Function 0 : Buffer full 1 : Buffer empty 0 : Buffer empty 1 : Buffer full 0 : Transmit shift in progress 1 : Transmit shift completed At reset RW 0 Transmit buffer empty flag 1 Receive buffer full flag (RBF) 2 Transmit shift register shift completion flag (TSC) 0 0 0 0 0 0 0 1 3 Overrun error flag (OE) 4 5 6 7 0 : No error 1 : Overrun error 0 : No error Parity error flag (PE) 1 : Parity error 0 : No error Framing error flag (FE) 1 : Framing error 0 : (OE) (PE) (FE) = 0 Summing error flag (SE) 1 : (OE) (PE) (FE) = 1 Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "1". Fig. 3.5.8 Structure of Serial I/O1 status register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-101 APPENDIX 7540 Group 3.5 List of registers Serial I/O1 control register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O1 control register (SIO1CON) [Address : 1A 16] B Name 0 : f(XIN) 1 : f(XIN)/4 Function At reset RW 0 BRG count source selection bit (CSS) selection bit (SCS) 0 0 1 Serial I/O1 synchronous clock When clock synchronous serial I/O is selected; 0: BRG output divided by 4 1: External clock input When UART is selected; 0: BRG output divided by 16 1: External clock input divided by 16 0: P13 pin 1: SRDY1 output pin 0 : Interrupt when transmit buffer has emptied 1 : Interrupt when transmit shift operation is completed 0 : Transmit disabled 1 : Transmit enabled 0 : Receive disabled 1 : Receive enabled 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O 0: Serial I/O1 disabled 1: Serial I/O1 enabled 2 SRDY1 output enable bit (SRDY) 3 Transmit interrupt source selection bit (TIC) 0 0 4 Transmit enable bit (TE) 5 Receive enable bit (RE) 6 Serial I/O1 mode selection bit (SIOM) 0 0 0 7 Serial I/O1 enable bit (SIOE) 0 Fig. 3.5.9 Structure of Serial I/O1 control register UART control register b7 b6 b5 b4 b3 b2 b1 b0 UART control register (UARTCON) [Address : 1B16] B 0 1 2 3 4 Name Character length selection bit (CHAS) Parity enable bit (PARE) Parity selection bit (PARS) Stop bit length selection bit (STPS) P11/TxD P-channel output disable bit (POFF) Function 0 : 8 bits 1 : 7 bits 0 : Parity checking disabled 1 : Parity checking enabled 0 : Even parity 1 : Odd parity 0 : 1 stop bit 1 : 2 stop bits In output mode 0 : CMOS output 1 : N-channel open-drain output At reset RW 0 0 0 0 0 5 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "1". 1 1 1 6 7 Fig. 3.5.10 Structure of UART control register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-102 APPENDIX 7540 Group 3.5 List of registers Baud rate generator b7 b6 b5 b4 b3 b2 b1 b0 Baud rate generator (BRG) [Address : 1C 16] B Function At reset RW 0 Set a count value of baud rate generator. 1 2 3 4 5 6 7 ? ? ? ? ? ? ? ? Fig. 3.5.11 Structure of Baud rate generator Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-103 APPENDIX 7540 Group 3.5 List of registers Timer A mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer A mode register (TAM) [Address : 1D 16] B Name Function At reset RW 0 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 0 0 0 0 1 2 3 4 Timer A operating mode bits 5 6 CNTR1 active edge switch bit b5 b4 0 0 1 1 0 : Timer mode 1 : Period measurement mode 0 : Event counter mode 1 : Pulse width HL continuously measurement mode 0 0 0 The function depends on the operating mode. (Refer to Table 3.5.1) 0 : Count start 1 : Count stop 7 Timer A count stop bit 0 Fig. 3.5.12 Structure of Timer A mode register Table 3.5.1 CNTR1 active edge switch bit function Timer A operating modes Timer mode CNTR1 active edge switch bit "0" CNTR1 interrupt request occurrence: Falling edge ; No influence to timer A count "1" CNTR1 interrupt request occurrence: Rising edge ; No influence to timer A count Period measurement mode "0" Pulse output start: Falling edge period measurement CNTR1 interrupt request occurrence: Falling edge "1" Pulse output start: Rising edge period measurement CNTR1 interrupt request occurrence: Rising edge Event counter mode "0" Timer A: Rising edge count CNTR1 interrupt request occurrence: Falling edge "1" Timer A: Falling edge count CNTR1 interrupt request occurrence: Rising edge Pulse width HL continuously measurement mode "0" CNTR1 interrupt request occurrence: Falling edge and rising edge ; No influence to timer A count "1" CNTR1 interrupt request occurrence: Rising edge and falling edge ; No influence to timer A count Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-104 APPENDIX 7540 Group 3.5 List of registers Timer A register (low-order, high-order) b7 b6 b5 b4 b3 b2 b1 b0 Timer A register (low-order, high-order) (TAL, TAH) [Address : 1E 16, 1F16] At reset B Function RW 0 *Set a count value of timer A. *The value set in this register is written to both timer A and timer A latch at the same time. *When this register is read out, the timer A's count value is read 2 out. 1 1 1 1 1 1 1 1 1 3 4 5 6 7 Notes 1: Be sure to write to/read out both the low-order of timer A (TAL) and the highorder of timer A (TAH). 2: Read the high-order of timer A (TAH) first, and the high-order of timer A (TAL) next. 3: Write to the low-order of timer A (TAL) first, and the high-order of timer A (TAH) next. 4: Do not write to them during read, and do not read out them during write. Fig. 3.5.13 Structure of Timer A register Timer Y, Z mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer Y, Z mode register (TYZM) [Address : 20 16) B 0 Name Timer Y operating mode bit Function 0 : Timer mode 1 : Programmable waveform generation mode At reset RW 0 1 Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "0". 0 : Write to latch and timer 2 Timer Y write control bit simultaneously (Note) 1 : Write to only latch 0 : Count start 3 Timer Y count stop bit 1 : Count stop 0 0 0 0 4 Timer Z operating mode bits b5 b4 5 0 0 : Timer mode 0 1 : Programmable waveform generation mode 1 0 : Programmable one-shot generation mode 1 1 : Programmable wait one-shot generation mode 0 : Write to latch and timer simultaneously 1 : Write to only latch 0 : Count start 1 : Count stop 0 6 Timer Z write control bit (Note) 0 7 Timer Z count stop bit 0 Note: When modes other than the timer mode, set these bits to "1". Fig. 3.5.14 Structure of Timer Y, Z mode register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-105 APPENDIX 7540 Group 3.5 List of registers Prescaler Y, Prescaler Z b7 b6 b5 b4 b3 b2 b1 b0 Prescaler Y (PREY) [Address : 2116] Prescaler Z (PREZ) [Address : 2516] B Function *While the corresponding timer is stopped, the value set in this register is written to both prescaler and the corresponding prescaler latch at the same time. *While the corresponding timer is operating, the value set in this register is written to as follows; When the timer write control bit is "0", the value is written to prescaler latch and prescaler at the same time. When the timer write control bit is "1", the value is written to prescaler latch only. *When this register is read out, the count value of the corresponding prescaler is read out. At reset RW 0 *Set a count value of each prescaler. 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 Fig. 3.5.15 Structure of Prescaler Y, Prescaler Z Timer Y secondary, Timer Z secondary b7 b6 b5 b4 b3 b2 b1 b0 Timer Y secondary, Timer Z secondary (TYS, TZS) [Address : 22 16, 2616] At reset B Function 0 *Set a count value of the corresponding timer. *The value set in this register is written to the corresponding 1 secondary latch at the same time. *These are read disabled bits. 2 When these bits are read out, the values are undefined. 1 1 1 1 1 1 1 1 RW 3 4 5 6 7 Fig. 3.5.16 Structure of Timer Y secondary, Timer Z secondary Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-106 APPENDIX 7540 Group 3.5 List of registers Timer Y primary, Timer Z primary b7 b6 b5 b4 b3 b2 b1 b0 Timer Y primary, Timer Z primary (TYP, TZP) [Address : 23 16, 2716] At reset B Function *When the corresponding timer is stopped, the value set in this register is written to both the corresponding primary latch and the corresponding timer at the same time. *When the corresponding timer is operating, the value set in this register is written as follows; timer write control bit = 0: the value is written to both the corresponding primary latch and the corresponding timer at the same time. timer write control bit = 1: the value is written to the corresponding primary latch. *When these bits are read out, the count value of the corresponding timer is read out (Note). RW 0 *Set a count value of the corresponding timer. 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 Note: The primary count value is read out at the primary interval, the secondary count value is read out at the secondary interval. Fig. 3.5.17 Structure of Timer Y primary, Timer Z primary Timer Y, Z waveform output control register b7 b6 b5 b4 b3 b2 b1 b0 Timer Y, Z waveform output control register (PUM) [Address : 24 16] At reset B 0 1 2 3 4 5 6 7 Name Timer Y primary waveform extension control bit Timer Y secondary waveform extension control bit Timer Z primary waveform extension control bit Timer Z secondary waveform extension control bit Function RW 0 : Waveform not extended 1 : Waveform extended 0 : Waveform not extended 1 : Waveform extended 0 : Waveform not extended 1 : Waveform extended 0 : Waveform not extended 1 : Waveform extended 0 : "L" output Timer Y output level latch 1 : "H" output 0 : "L" output Timer Z output level latch 1 : "H" output 0 : INT0 pin one-shot trigger invalid INT0 pin one-shot trigger 1 : INT0 pin one-shot trigger valid control bit (Note) INT0 pin one-shot trigger active 0 : Falling edge trigger 1 : Rising edge trigger edge selection bit ( Note) 0 0 0 0 0 0 0 0 Note: Stop timer Z to change the values of these bits. Fig. 3.5.18 Structure of Timer Y, Z waveform output control register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-107 APPENDIX 7540 Group 3.5 List of registers Prescaler 1 b7 b6 b5 b4 b3 b2 b1 b0 Prescaler 1 (PRE1) [Address : 2816] B Function At reset RW 0 *Set a count value of prescaler 1. *The value set in this register is written to both prescaler 1 1 and the prescaler 1 latch at the same time. *When this register is read out, the count value of the prescaler 1 2 is read out. 1 1 1 1 1 1 1 1 3 4 5 6 7 Fig. 3.5.19 Structure of Prescaler 1 Timer 1 b7 b6 b5 b4 b3 b2 b1 b0 Timer 1 (T1) [Address : 2916] B Function At reset RW 0 *Set a count value of timer 1. *The value set in this register is written to both timer 1 and timer 1 1 latch at the same time. *When this register is read out, the timer 1's count value is read 2 out. 1 0 0 0 0 0 0 0 3 4 5 6 7 Fig. 3.5.20 Structure of Timer 1 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-108 APPENDIX 7540 Group 3.5 List of registers One-shot start register b7 b6 b5 b4 b3 b2 b1 b0 One-shot start register (ONS) [Address : 2A 16] B Name Function 0 : One-shot stop 1 : One-shot start At reset RW 0 Timer Z one-shot start bit 0 0 0 0 0 0 0 0 1 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 2 3 4 5 6 7 Fig. 3.5.21 Structure of One-shot start register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-109 APPENDIX 7540 Group 3.5 List of registers Timer X mode register b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register (TXM) [Address : 2B 16] B 0 Name Timer X operating mode bits b1 b0 Function 0 0 1 1 0 : Timer mode 1 : Pulse output mode 0 : Event counter mode 1 : Pulse width measurement mode At reset RW 0 1 2 CNTR0 active edge switch bit 0 0 The function depends on the operating mode. (Refer to Table 3.5.2) 0 : Count start 1 : Count stop 0 : Output invalid (I/O port) 1 : Output valid (Inverted CNTR 0 output) 3 Timer X count stop bit 4 P03/TXOUT output valid bit 0 0 5 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 0 0 0 6 7 Fig. 3.5.22 Structure of Timer X mode register Table 3.5.2 CNTR0 active edge switch bit function Timer X operating modes Timer mode CNTR0 active edge switch bit (bit 2 of address 2B16) contents "0" CNTR0 interrupt request occurrence: Falling edge ; No influence to timer count "1" CNTR0 interrupt request occurrence: Rising edge ; No influence to timer count Pulse output mode "0" Pulse output start: Beginning at "H" level CNTR0 interrupt request occurrence: Falling edge "1" Pulse output start: Beginning at "L" level CNTR0 interrupt request occurrence: Rising edge Event counter mode "0" Timer X: Rising edge count CNTR0 interrupt request occurrence: Falling edge "1" Timer X: Falling edge count CNTR0 interrupt request occurrence: Rising edge Pulse width measurement mode "0" Timer X: "H" level width measurement CNTR0 interrupt request occurrence: Falling edge "1" Timer X: "L" level width measurement CNTR0 interrupt request occurrence: Rising edge Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-110 APPENDIX 7540 Group 3.5 List of registers Prescaler X b7 b6 b5 b4 b3 b2 b1 b0 Prescaler X (PREX) [Address : 2C 16] B Function At reset RW 0 *Set a count value of prescaler X. *The value set in this register is written to both prescaler X and the prescaler X latch at the same time. *When this register is read out, the count value of the prescaler X 2 is read out. 1 1 1 1 1 1 1 1 1 3 4 5 6 7 Fig. 3.5.23 Structure of Prescaler X Timer X b7 b6 b5 b4 b3 b2 b1 b0 Timer X (TX) [Address : 2D 16] B Function At reset RW 0 *Set a count value of timer X. *The value set in this register is written to both timer X and timer X latch at the same time. *When this register is read out, the timer X's count value is read 2 out. 1 1 1 1 1 1 1 1 1 3 4 5 6 7 Fig. 3.5.24 Structure of Timer X Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-111 APPENDIX 7540 Group 3.5 List of registers Timer count source set register b7 b6 b5 b4 b3 b2 b1 b0 0 Timer count source set register (TCSS) [Address : 2E16] B Name b1 b0 Function 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : f(XIN) (Note 1) 1 1 : Not available b3 b2 At reset RW 0 Timer X count source selection bits 1 2 Timer Y count source selection bits 0 0 0 0 0 0 0 0 3 4 Timer Z count source selection bits 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : On-chip oscillator output (Note 2) 1 1 : Not available b5 b4 5 6 Fix this bit to "0". 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : Timer Y underflow 1 1 : Not available 7 Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "0". Notes 1: f(XIN) can be used as timer X count source only when using a ceramic oscillator or on-chip oscillator. Do not use it at RC oscillation. 2: System operates using an on-chip oscillator as a count source by setting the on-chip oscillator to oscillation enabled by bit 3 of CPUM. Fig. 3.5.25 Structure of Timer count source set register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-112 APPENDIX 7540 Group 3.5 List of registers Serial I/O2 control register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O2 control register (SIO2CON) [Address : 3016] B Name b2 b1 b0 Function At reset RW 0 Internal synchronous clock selection bits 1 2 3 4 5 6 7 0 0 0 : f(XIN)/8 0 0 1 : f(XIN)/16 0 1 0 : f(XIN)/32 0 1 1 : f(XIN)/64 1 1 0 : f(XIN)/128 1 1 1 : f(XIN)/256 SDATA2 pin selection bit 0 : I/O port / SDATA2 input (Note) 1 : SDATA2 output Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "0". Transfer direction selection bit 0 : LSB first 1 : MSB first 0 : External clock (SCLK2 is input) SCLK2 pin selection bit 1 : Internal clock (SCLK2 is output) Transmit / receive shift 0 : shift in progress completion flag 1 : shift completed 0 0 0 0 0 0 0 0 Note: When using it as a SDATA input, set the port P13 direction register bit to "0". Fig. 3.5.26 Structure of Serial I/O2 control register Serial I/O2 register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O2 register (SIO2) [Address : 31 16] B Function * At transmitting : Set a transmission data. At reset RW 0 A shift register for serial transmission and reception. 1 * At receiving : A reception data is stored. 2 3 4 5 6 7 ? ? ? ? ? ? ? ? Fig. 3.5.27 Structure of Serial I/O2 register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-113 APPENDIX 7540 Group 3.5 List of registers A/D control register b7 b6 b5 b4 b3 b2 b1 b0 A/D control register (ADCON) [Address : 3416] B 0 1 2 3 4 5 6 7 Name Analog input pin selection bits b2 b1 b0 Function 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : P20/AN0 1 : P21/AN1 0 : P22/AN2 1 : P23/AN3 0 : P24/AN4 1 : P25/AN5 0 : P26/AN6 1 : P27/AN7 At reset RW 0 0 (Note) (Note) 0 0 1 0 0 0 Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "0". AD conversion completion bit 0 : Conversion in progress 1 : Conversion completed Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". Note: These can be used only for the 36-pin package versions. : This bit can be cleared to "0" by program, but cannot be set to "1". Fig. 3.5.28 Structure of A/D control register A/D conversion register (low-order) b7 b6 b5 b4 b3 b2 b1 b0 A/D conversion register (low-order) (ADL) [Address : 3516] B stored. Function At reset RW 0 The read-only register in which the A/D conversion's results are 1 2 3 4 b7 b7 < 8-bit read> b0 ? ? ? ? ? b9 b8 b7 b6 b5 b4 b3 b2 < 10-bit read> b0 5 6 7 b7 b6 b5 b4 b3 b2 b1 b0 ? ? ? Fig. 3.5.29 Structure of A/D conversion register (low-order) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-114 APPENDIX 7540 Group 3.5 List of registers A/D conversion register (high-order) b7 b6 b5 b4 b3 b2 b1 b0 A/D conversion register (high-order) (ADH) [Address : 3616] B stored. Function At reset RW 0 The read-only register in which the A/D conversion's results are 1 b7 < 10-bit read> b0 b9 b8 ? ? ? ? ? ? ? ? 2 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 3 4 5 6 7 Fig. 3.5.30 Structure of A/D conversion register (high-order) MISRG b7 b6 b5 b4 b3 b2 b1 b0 MISRG [Address : 3816] B Name set bit after release of the STP instruction Function 0 : Set "0116" in timer 1, and "FF16" in prescaler 1 automatically 1 : Not set automatically 1 : Detection function active At reset RW 0 Oscillation stabilization time 0 1 Ceramic or RC oscillation stop 0 : Detection function inactive detection function active bit 2 These are reserved bits. Do not write "1" to these bits. 0 0 0 3 4 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 0 0 0 5 6 7 Oscillation stop detection status bit 0 : Oscillation stop not detected 1 : Oscillation stop detected (Note) Note: "0" at normal reset "1" at reset by detecting the oscillation stop Fig. 3.5.31 Structure of MISRG Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-115 APPENDIX 7540 Group 3.5 List of registers Watchdog timer control register b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer control register (WDTCON) [Address : 39 16] B Name (The high-order 6 bits are read-only bits.) Function At reset RW 0 Watchdog timer H 1 2 3 4 5 6 STP instruction disable bit 7 Watchdog timer H count source selection bit 0 : STP instruction enabled 1 : STP instruction disabled 0 : Watchdog timer L underflow 1 : f(XIN)/16 1 1 1 1 1 1 0 0 Fig. 3.5.32 Structure of Watchdog timer control register Interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 Interrupt edge selection register (INTEDGE) [Address : 3A 16] B Name Function 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active At reset RW 0 INT0 interrupt edge selection bit 1 INT1 interrupt edge selection bit 0 0 0 0 0 0 0 2 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 3 4 5 6 7 P00 key-on wakeup enable bit 0 : Key-on wakeup enabled 1 : Key-on wakeup disabled 0 Fig. 3.5.33 Structure of Interrupt edge selection register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-116 APPENDIX 7540 Group 3.5 List of registers CPU mode register b7 b6 b5 b4 b3 b2 b1 b0 CPU mode register (CPUM) [Address : 3B16] B Name b1 b0 Function 0 0 1 1 0 : Single-chip mode 1 : Not available 0 : Not available 1 : Not available At reset RW 0 Processor mode bits (Note 1) 1 2 Stack page selection bit 0 0 0 0 0 0 0 3 On-chip oscillator oscillation control bit XIN oscillation control bit 4 (Note 1) 5 Oscillation mode selection bit 6 Clock division ratio selection bits 0 : 0 page 1 : 1 page 0 : On-chip oscillator oscillation enabled 1 : On-chip oscillator oscillation stop 0 : Ceramic or RC oscillation enabled 1 : Ceramic or RC oscillation stop 0 : Ceramic oscillation 1 : RC oscillation b7 b6 7 0 0 : = f(XIN)/2 (high-speed mode) 0 1 : = f(XIN)/8 (middle-speed mode) 1 0 : Applied from on-chip oscillator 1 1 : = f(XIN) (double-speed mode) (Note 2) 1 Notes 1: The bit can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. However, by reset the bit is initialized and can be rewritten, again. (It is not disable to write any data to the bit for emulator MCU "M37540RSS".) 2: These bits are used only when a ceramic oscillation is selected. Do not use these when an RC oscillation is selected. Fig. 3.5.34 Structure of CPU mode register Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-117 APPENDIX 7540 Group 3.5 List of registers Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address : 3C 16] B Name Function 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset RW 0 Serial I/O1 receive interrupt request bit 1 Serial I/O1 transmit interrupt request bit 2 INT0 interrupt request bit 3 INT1 interrupt request bit 4 Key-on wake up interrupt request bit 5 CNTR0 interrupt request bit 0 0 0 0 0 0 0 0 6 CNTR1 interrupt request bit 7 Timer X interrupt request bit : These bits can be cleared to "0" by program, but cannot be set to "1". Fig. 3.5.35 Structure of Interrupt request register 1 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2) [Address : 3D 16] B Name Function 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued At reset RW 0 Timer Y interrupt request bit 1 Timer Z interrupt request bit 2 Timer A interrupt request bit 3 Serial I/O2 interrupt request bit 4 AD converter interrupt request bit 0 0 0 0 0 0 0 0 5 Timer 1 interrupt request bit 6 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 7 : These bits can be cleared to "0" by program, but cannot be set to "1". Fig. 3.5.36 Structure of Interrupt request register 2 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-118 APPENDIX 7540 Group 3.5 List of registers Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address : 3E 16] B Name Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset RW 0 Serial I/O1 receive interrupt enable bit 1 Serial I/O1 transmit interrupt enable bit 0 0 0 0 0 0 0 0 2 INT0 interrupt enable bit 3 INT1 interrupt enable bit 4 Key-on wake up interrupt enable bit 5 CNTR0 interrupt enable bit 6 CNTR1 interrupt enable bit 7 Timer X interrupt enable bit Fig. 3.5.37 Structure of Interrupt control register 1 Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 2 (ICON2) [Address : 3F 16] B Name Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled At reset RW 0 Timer Y interrupt enable bit 1 Timer Z interrupt enable bit 2 Timer A interrupt enable bit 3 Serial I/O2 interrupt enable bit 4 AD conversion interrupt enable bit 5 Timer 1 interrupt enable bit 0 0 0 0 0 0 0 0 6 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0". 7 Fig. 3.5.38 Structure of Interrupt control register 2 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-119 APPENDIX 7540 Group 3.6 Package outline 3.6 Package outline 32P4B EIAJ Package Code SDIP32-P-400-1.78 Recommended JEDEC Code - Weight(g) 2.2 Lead Material Alloy 42/Cu Alloy Plastic 32pin 400mil SDIP 32 17 1 16 D Symbol A A1 A2 b b1 b2 c D E e e1 L e SEATING PLANE b1 b b2 Dimension in Millimeters Min Nom Max - - 5.08 0.51 - - - 3.8 - 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 27.8 28.0 28.2 8.75 8.9 9.05 - 1.778 - - 10.16 - 3.0 - - 0 - 15 A 32P6U-A L Recommended JEDEC Code - HD D 32 25 A1 A2 Plastic 32pin 77mm body LQFP Weight(g) Lead Material Cu Alloy e EIAJ Package Code LQFP32-P-0707-0.80 MD e1 E c I2 1 24 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 Lp A3 8 17 9 16 E HE A L1 A2 A3 e F A1 L Lp b c x y b2 I2 MD ME x M y Detail F b2 Dimension in Millimeters Min Nom Max - - 1.7 0.1 0.2 0 - - 1.4 0.32 0.37 0.45 0.105 0.125 0.175 6.9 7.0 7.1 6.9 7.0 7.1 0.8 - - 8.8 9.0 9.2 8.8 9.0 9.2 0.3 0.5 0.7 1.0 - - 0.45 0.6 0.75 - 0.25 - - - 0.2 0.1 - - 0 10 - 0.5 - - 1.0 - - 7.4 - - - - 7.4 ME Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-120 APPENDIX 7540 Group 3.6 Package outline 36P2R-A EIAJ Package Code SSOP36-P-450-0.80 36 Recommended JEDEC Code - Weight(g) 0.53 19 Plastic 36pin 450mil SSOP Lead Material Alloy 42 e b2 HE E e1 F Recommended Mount Pad Dimension in Millimeters Min Nom Max 2.4 - - - - 0.05 - 2.0 - 0.5 0.4 0.35 0.2 0.15 0.13 15.2 15.0 14.8 8.6 8.4 8.2 - 0.8 - 12.23 11.93 11.63 0.7 0.5 0.3 - 1.765 - - 0.7 - - - 0.85 0.15 - - 0 - 10 - 0.5 - - 11.43 - - 1.27 - Symbol 1 18 A G D A2 e y b A1 A A1 A2 b c D E e HE L L1 z Z1 y b2 e1 I2 L1 z Z1 Detail G Detail F L c I2 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-121 APPENDIX 7540 Group 3.7 Machine instructions 3.7 Machine instructions Addressing mode Symbol Function Details IMP OP n ADC (Note 1) (Note 5) When T = 0 AA+M+C When T = 1 M(X) M(X) + M + C When T = 0, this instruction adds the contents M, C, and A; and stores the results in A and C. When T = 1, this instruction adds the contents of M(X), M and C; and stores the results in M(X) and C. When T=1, the contents of A remain unchanged, but the contents of status flags are changed. M(X) represents the contents of memory where is indicated by X. When T = 0, this instruction transfers the contents of A and M to the ALU which performs a bit-wise AND operation and stores the result back in A. When T = 1, this instruction transfers the contents M(X) and M to the ALU which performs a bit-wise AND operation and stores the results back in M(X). When T = 1, the contents of A remain unchanged, but status flags are changed. M(X) represents the contents of memory where is indicated by X. This instruction shifts the content of A or M by one bit to the left, with bit 0 always being set to 0 and bit 7 of A or M always being contained in C. This instruction tests the designated bit i of M or A and takes a branch if the bit is 0. The branch address is specified by a relative address. If the bit is 1, next instruction is executed. This instruction tests the designated bit i of the M or A and takes a branch if the bit is 1. The branch address is specified by a relative address. If the bit is 0, next instruction is executed. This instruction takes a branch to the appointed address if C is 0. The branch address is specified by a relative address. If C is 1, the next instruction is executed. This instruction takes a branch to the appointed address if C is 1. The branch address is specified by a relative address. If C is 0, the next instruction is executed. This instruction takes a branch to the appointed address when Z is 1. The branch address is specified by a relative address. If Z is 0, the next instruction is executed. This instruction takes a bit-wise logical AND of A and M contents; however, the contents of A and M are not modified. The contents of N, V, Z are changed, but the contents of A, M remain unchanged. This instruction takes a branch to the appointed address when N is 1. The branch address is specified by a relative address. If N is 0, the next instruction is executed. This instruction takes a branch to the appointed address if Z is 0. The branch address is specified by a relative address. If Z is 1, the next instruction is executed. 24 3 2 IMM # OP n 69 2 A # OP n 2 BIT, A BIT, A, R # OP n ZP BIT, ZP BIT, ZP, R # OP n 2 # # OP n 65 3 ASL C 7 0 0 BBC (Note 4) Ai or Mi = 0? BBS (Note 4) Ai or Mi = 1? BCC (Note 4) C = 0? BCS (Note 4) C = 1? BEQ (Note 4) Z = 1? BIT A M BMI (Note 4) N = 1? BNE (Note 4) Z = 0? Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z V When T = 1 M(X) M(X) V AND (Note 1) When T = 0 AA M M 29 2 2 25 3 2 0A 2 1 06 5 2 13 4 + 20i 2 17 5 + 20i 3 03 4 + 20i 2 07 5 + 20i 3 V 3-122 APPENDIX 7540 Group 3.7 Machine instructions Addressing mode ZP, X OP n 75 4 ZP, Y # OP n 2 ABS # OP n 6D 4 ABS, X # OP n 3 7D 5 ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7 Processor status register 6 V V 5 T * 4 B * 3 D * 2 I * 1 Z Z 0 C C # OP n 3 79 5 # OP n 3 # OP n 61 6 # OP n 2 71 6 # OP n 2 N N 35 4 2 2D 4 3 3D 5 3 39 5 3 21 6 2 31 6 2 N * * * * * Z * 16 6 2 0E 6 3 1E 7 3 N * * * * * Z C * * * * * * * * * * * * * * * * 90 2 2 * * * * * * * * B0 2 2 * * * * * * * * F0 2 2 * * * * * * * * 2C 4 3 M7 M6 * * * * Z * 30 2 2 * * * * * * * * D0 2 2 * * * * * * * * Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-123 APPENDIX 7540 Group 3.7 Machine instructions Addressing mode Symbol Function Details IMP OP n BPL (Note 4) N = 0? This instruction takes a branch to the appointed address if N is 0. The branch address is specified by a relative address. If N is 1, the next instruction is executed. This instruction branches to the appointed address. The branch address is specified by a relative address. When the BRK instruction is executed, the CPU pushes the current PC contents onto the stack. The BADRS designated in the interrupt vector table is stored into the PC. 00 7 1 IMM # OP n A # OP n BIT, A # OP n ZP # OP n BIT, ZP # OP n # BRA PC PC offset BRK B1 (PC) (PC) + 2 M(S) PCH SS-1 M(S) PCL SS-1 M(S) PS SS-1 I 1 PCL ADL PCH ADH V = 0? BVC (Note 4) This instruction takes a branch to the appointed address if V is 0. The branch address is specified by a relative address. If V is 1, the next instruction is executed. This instruction takes a branch to the appointed address when V is 1. The branch address is specified by a relative address. When V is 0, the next instruction is executed. This instruction clears the designated bit i of A or M. This instruction clears C. 18 2 1 1B 2 + 20i 1 1F 5 + 20i 2 BVS (Note 4) V = 1? CLB Ai or Mi 0 C0 D0 I0 T0 V0 When T = 0 A-M When T = 1 M(X) - M CLC CLD This instruction clears D. D8 2 1 CLI This instruction clears I. 58 2 1 CLT This instruction clears T. 12 2 1 CLV This instruction clears V. B8 2 1 CMP (Note 3) When T = 0, this instruction subtracts the contents of M from the contents of A. The result is not stored and the contents of A or M are not modified. When T = 1, the CMP subtracts the contents of M from the contents of M(X). The result is not stored and the contents of X, M, and A are not modified. M(X) represents the contents of memory where is indicated by X. This instruction takes the one's complement of the contents of M and stores the result in M. This instruction subtracts the contents of M from the contents of X. The result is not stored and the contents of X and M are not modified. This instruction subtracts the contents of M from the contents of Y. The result is not stored and the contents of Y and M are not modified. This instruction subtracts 1 from the contents of A or M. C9 2 2 C5 3 2 COM MM __ 44 5 2 CPX X-M E0 2 2 E4 3 2 CPY Y-M C0 2 2 C4 3 2 DEC A A - 1 or MM-1 1A 2 1 C6 5 2 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-124 APPENDIX 7540 Group 3.7 Machine instructions Addressing mode ZP, X OP n ZP, Y # OP n ABS # OP n ABS, X # OP n ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n 2 # 7 Processor status register 6 V * 5 T * 4 B * 3 D * 2 I * 1 Z * 0 C * # OP n # OP n # OP n # OP n # OP n 10 2 N * 80 4 2 * * * * * * * * * * * 1 * 1 * * 50 2 2 * * * * * * * * 70 2 2 * * * * * * * * * * * * * * * * * * * * * * * 0 * * * * 0 * * * * * * * * 0 * * * * 0 * * * * * * D5 4 2 CD 4 3 DD 5 3 D9 5 3 C1 6 2 D1 6 2 0 * * * * * * N * * * * * Z C N EC 4 3 * * * * * Z * N * * * * * Z C CC 4 3 N * * * * * Z C D6 6 2 CE 6 3 DE 7 3 N * * * * * Z * Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-125 APPENDIX 7540 Group 3.7 Machine instructions Addressing mode Symbol Function Details IMP OP n DEX XX-1 YY-1 A (M(zz + X + 1), M(zz + X )) / A M(S) one's complement of Remainder SS-1 When T = 0 - A AVM When T = 1 - M(X) M(X) V M This instruction subtracts one from the current CA 2 contents of X. This instruction subtracts one from the current contents of Y. This instruction divides the 16-bit data in M(zz+(X)) (low-order byte) and M(zz+(X)+1) (high-order byte) by the contents of A. The quotient is stored in A and the one's complement of the remainder is pushed onto the stack. When T = 0, this instruction transfers the contents of the M and A to the ALU which performs a bit-wise Exclusive OR, and stores the result in A. When T = 1, the contents of M(X) and M are transferred to the ALU, which performs a bitwise Exclusive OR and stores the results in M(X). The contents of A remain unchanged, but status flags are changed. M(X) represents the contents of memory where is indicated by X. This instruction adds one to the contents of A or M. This instruction adds one to the contents of X. E8 2 C8 2 1 49 2 2 45 3 2 88 2 IMM # OP n 1 A # OP n BIT, A # OP n ZP # OP n BIT, ZP # OP n # DEY 1 DIV EOR (Note 1) INC A A + 1 or MM+1 XX+1 YY+1 If addressing mode is ABS PCL ADL PCH ADH If addressing mode is IND PCL M (ADH, ADL) PCH M (ADH, ADL + 1) If addressing mode is ZP, IND PCL M(00, ADL) PCH M(00, ADL + 1) M(S) PCH SS-1 M(S) PCL SS-1 After executing the above, if addressing mode is ABS, PCL ADL PCH ADH if addressing mode is SP, PCL ADL PCH FF If addressing mode is ZP, IND, PCL M(00, ADL) PCH M(00, ADL + 1) When T = 0 AM When T = 1 M(X) M 3A 2 1 E6 5 2 INX INY JMP This instruction adds one to the contents of Y. This instruction jumps to the address designated by the following three addressing modes: Absolute Indirect Absolute Zero Page Indirect Absolute 1 JSR This instruction stores the contents of the PC in the stack, then jumps to the address designated by the following addressing modes: Absolute Special Page Zero Page Indirect Absolute LDA (Note 2) When T = 0, this instruction transfers the contents of M to A. When T = 1, this instruction transfers the contents of M to (M(X)). The contents of A remain unchanged, but status flags are changed. M(X) represents the contents of memory where is indicated by X. This instruction loads the immediate value in M. This instruction loads the contents of M in X. This instruction loads the contents of M in Y. A9 2 2 A5 3 2 LDM M nn XM YM 3C 4 3 LDX LDY A2 2 A0 2 2 2 A6 3 A4 3 2 2 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-126 APPENDIX 7540 Group 3.7 Machine instructions Addressing mode ZP, X OP n ZP, Y # OP n ABS # OP n ABS, X # OP n ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7 Processor status register 6 V * 5 T * 4 B * 3 D * 2 I * 1 Z Z 0 C * # OP n # OP n # OP n # OP n # OP n N N N * * * * * Z * E2 16 2 * * * * * * * * 55 4 2 4D 4 3 5D 5 3 59 5 3 41 6 2 51 6 2 N * * * * * Z * F6 6 2 EE 6 3 FE 7 3 N * * * * * Z * N * * * * * Z * N 4C 3 3 6C 5 3 B2 4 2 * * * * * * * * * * * Z * * * 20 6 3 02 7 2 22 5 2 * * * * * * * * B5 4 2 AD 4 3 BD 5 3 B9 5 3 A1 6 2 B1 6 2 N * * * * * Z * * * * * * * * * B6 4 B4 4 2 2 AE 4 AC 4 3 3 BC 5 3 BE 5 3 N N * * * * * * * * * * Z Z * * Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-127 APPENDIX 7540 Group 3.7 Machine instructions Addressing mode Symbol Function Details IMP OP n LSR 7 0 0 C This instruction shifts either A or M one bit to the right such that bit 7 of the result always is set to 0, and the bit 0 is stored in C. This instruction multiply Accumulator with the memory specified by the Zero Page X address mode and stores the high-order byte of the result on the Stack and the low-order byte in A. This instruction adds one to the PC but does EA 2 no otheroperation. When T = 0, this instruction transfers the contents of A and M to the ALU which performs a bit-wise "OR", and stores the result in A. When T = 1, this instruction transfers the contents of M(X) and the M to the ALU which performs a bit-wise OR, and stores the result in M(X). The contents of A remain unchanged, but status flags are changed. M(X) represents the contents of memory where is indicated by X. This instruction pushes the contents of A to the memory location designated by S, and decrements the contents of S by one. This instruction pushes the contents of PS to the memory location designated by S and decrements the contents of S by one. This instruction increments S by one and stores the contents of the memory designated by S in A. This instruction increments S by one and stores the contents of the memory location designated by S in PS. This instruction shifts either A or M one bit left through C. C is stored in bit 0 and bit 7 is stored in C. 48 3 1 1 09 2 2 05 3 2 IMM # OP n A # OP n 4A 2 BIT, A # OP n 1 ZP # OP n 46 5 BIT, ZP # OP n 2 # MUL M(S) * A A M(zz + X) SS-1 NOP PC PC + 1 When T = 0 AAVM When T = 1 M(X) M(X) V M ORA (Note 1) PHA M(S) A SS-1 PHP M(S) PS SS-1 SS+1 A M(S) SS+1 PS M(S) 08 3 1 PLA 68 4 1 PLP 28 4 1 ROL 7 0 C 2A 2 1 26 5 2 ROR 7 C 0 This instruction shifts either A or M one bit right through C. C is stored in bit 7 and bit 0 is stored in C. 6A 2 1 66 5 2 RRF 7 SS+1 PS M(S) SS+1 PCL M(S) SS+1 PCH M(S) 0 This instruction rotates 4 bits of the M content to the right. 82 8 2 RTI This instruction increments S by one, and stores the contents of the memory location designated by S in PS. S is again incremented by one and stores the contents of the memory location designated by S in PCL. S is again incremented by one and stores the contents of memory location designated by S in PCH. This instruction increments S by one and stores the contents of the memory location d e s i g n a t e d b y S i n P C L. S i s a g a i n incremented by one and the contents of the memory location is stored in PCH. PC is incremented by 1. 40 6 1 RTS SS+1 PCL M(S) SS+1 PCH M(S) (PC) (PC) + 1 60 6 1 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-128 APPENDIX 7540 Group 3.7 Machine instructions Addressing mode ZP, X OP n 56 6 ZP, Y # OP n 2 ABS # OP n 4E 6 ABS, X # OP n 3 5E 7 ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7 Processor status register 6 V * 5 T * 4 B * 3 D * 2 I * 1 Z Z 0 C C # OP n 3 # OP n # OP n # OP n # OP n N 0 62 15 2 * * * * * * * * * * * * * * * * 15 4 2 0D 4 3 1D 5 3 19 5 3 01 6 2 11 6 2 N * * * * * Z * * * * * * * * * * * * * * * * * N * * * * * Z * (Value saved in stack) 36 6 2 2E 6 3 3E 7 3 N * * * * * Z C 76 6 2 6E 6 3 7E 7 3 N * * * * * Z C * * * * * * * * (Value saved in stack) * * * * * * * * Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-129 APPENDIX 7540 Group 3.7 Machine instructions Addressing mode Symbol Function Details IMP OP n SBC (Note 1) (Note 5) When T = 0 _ AA-M-C When T = 1 _ M(X) M(X) - M - C When T = 0, this instruction subtracts the value of M and the complement of C from A, and stores the results in A and C. When T = 1, the instruction subtracts the contents of M and the complement of C from the contents of M(X), and stores the results in M(X) and C. A remain unchanged, but status flag are changed. M(X) represents the contents of memory where is indicated by X. This instruction sets the designated bit i of A or M. This instruction sets C. 38 2 F8 2 78 2 32 2 1 IMM # OP n E9 2 A # OP n 2 BIT, A # OP n ZP # OP n E5 3 BIT, ZP # OP n 2 # SEB Ai or Mi 1 C1 D1 I1 T1 MA 0B 2 + 20i 1 0F 5 + 20i 2 SEC SED This instruction set D. 1 SEI This instruction set I. 1 SET This instruction set T. 1 85 4 2 STA This instruction stores the contents of A in M. The contents of A does not change. This instruction resets the oscillation control F/ F and the oscillation stops. Reset or interrupt input is needed to wake up from this mode. 42 2 1 STP STX MX MY XA YA M = 0? XS AX SX AY This instruction stores the contents of X in M. The contents of X does not change. This instruction stores the contents of Y in M. The contents of Y does not change. This instruction stores the contents of A in X. AA 2 The contents of A does not change. This instruction stores the contents of A in Y. The contents of A does not change. This instruction tests whether the contents of M are "0" or not and modifies the N and Z. This instruction transfers the contents of S in BA 2 X. This instruction stores the contents of X in A. 8A 2 1 A8 2 1 86 4 84 4 2 STY 2 TAX TAY 1 64 3 2 TST TSX TXA 1 TXS This instruction stores the contents of X in S. 9A 2 1 TYA This instruction stores the contents of Y in A. 98 2 1 WIT The WIT instruction stops the internal clock but not the oscillation of the oscillation circuit is not stopped. CPU starts its function after the Timer X over flows (comes to the terminal count). All registers or internal memory contents except Timer X will not change during this mode. (Of course needs VDD). C2 2 1 Notes 1 2 3 4 5 : : : : : The number of cycles "n" is increased by 3 when T is 1. The number of cycles "n" is increased by 2 when T is 1. The number of cycles "n" is increased by 1 when T is 1. The number of cycles "n" is increased by 2 when branching has occurred. N, V, and Z flags are invalid in decimal operation mode. Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-130 APPENDIX 7540 Group 3.7 Machine instructions Addressing mode ZP, X OP n F5 4 ZP, Y # OP n 2 ABS # OP n ED 4 ABS, X # OP n 3 FD 5 ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7 Processor status register 6 V V 5 T * 4 B * 3 D * 2 I * 1 Z Z 0 C C # OP n 3 F9 5 # OP n 3 # OP n E1 6 # OP n 2 F1 6 # OP n 2 N N * * * * * * * * * * * * * * * 1 * * * * 1 * * * * * * * * 1 * * * 95 5 2 8D 5 3 9D 6 3 99 6 3 81 7 2 91 7 2 * * * 1 * * * * * * * * * * * * * * * * * * * 96 5 94 5 2 8E 5 3 * * * * * * * * 2 8C 5 3 * * * * * * * * N * * * * * Z * N * * * * * Z * N * * * * * Z * N * * * * * Z * N * * * * * Z * * * * * * * * * N * * * * * Z * * * * * * * * * Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-131 APPENDIX 7540 Group 3.7 Machine instructions Symbol IMP IMM A BIT, A BIT, A, R ZP BIT, ZP BIT, ZP, R ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP C Z I D B T V N Contents Implied addressing mode Immediate addressing mode Accumulator or Accumulator addressing mode Accumulator bit addressing mode Accumulator bit relative addressing mode Zero page addressing mode Zero page bit addressing mode Zero page bit relative addressing mode Zero page X addressing mode Zero page Y addressing mode Absolute addressing mode Absolute X addressing mode Absolute Y addressing mode Indirect absolute addressing mode Zero page indirect absolute addressing mode Indirect X addressing mode Indirect Y addressing mode Relative addressing mode Special page addressing mode Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag X-modified arithmetic mode flag Overflow flag Negative flag + - / V V - V - X Y S PC PS PCH PCL ADH ADL FF nn zz M Symbol Contents Addition Subtraction Multiplication Division Logical OR Logical AND Logical exclusive OR Negation Shows direction of data flow Index register X Index register Y Stack pointer Program counter Processor status register 8 high-order bits of program counter 8 low-order bits of program counter 8 high-order bits of address 8 low-order bits of address FF in Hexadecimal notation Immediate value Zero page address Memory specified by address designation of any addressing mode Memory of address indicated by contents of index register X Memory of address indicated by contents of stack pointer Contents of memory at address indicated by ADH and ADL, in ADH is 8 high-order bits and ADL is 8 low-order bits. Contents of address indicated by zero page ADL Bit i (i = 0 to 7) of accumulator Bit i (i = 0 to 7) of memory Opcode Number of cycles Number of bytes M(X) M(S) M(ADH, ADL) M(00, ADL) Ai Mi OP n # Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-132 APPENDIX 7540 Group 3.8 List of instruction code 3.8 List of instruction code D3 - D0 Hexadecimal notation 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 D7 - D4 0 1 2 3 4 5 ORA ZP ORA ZP, X AND ZP AND ZP, X EOR ZP EOR ZP, X ADC ZP ADC ZP, X STA ZP STA ZP, X LDA ZP LDA ZP, X CMP ZP CMP ZP, X SBC ZP SBC ZP, X 6 ASL ZP ASL ZP, X ROL ZP ROL ZP, X LSR ZP LSR ZP, X ROR ZP ROR ZP, X STX ZP STX ZP, Y LDX ZP LDX ZP, Y DEC ZP DEC ZP, X INC ZP INC ZP, X 7 BBS 0, ZP BBC 0, ZP BBS 1, ZP BBC 1, ZP BBS 2, ZP BBC 2, ZP BBS 3, ZP BBC 3, ZP BBS 4, ZP BBC 4, ZP BBS 5, ZP BBC 5, ZP BBS 6, ZP BBC 6, ZP BBS 7, ZP BBC 7, ZP 8 9 ORA IMM ORA ABS, Y AND IMM AND ABS, Y EOR IMM EOR ABS, Y ADC IMM ADC ABS, Y -- STA ABS, Y LDA IMM LDA ABS, Y CMP IMM CMP ABS, Y SBC IMM SBC ABS, Y A ASL A DEC A ROL A INC A LSR A -- ROR A -- B SEB 0, A CLB 0, A SEB 1, A CLB 1, A SEB 2, A CLB 2, A SEB 3, A CLB 3, A SEB 4, A CLB 4, A SEB 5, A CLB 5, A SEB 6, A CLB 6, A SEB 7, A CLB 7, A C D ORA ABS E ASL ABS F SEB 0, ZP 0000 BRK BBS ORA JSR IND, X ZP, IND 0, A ORA IND, Y AND IND, X AND IND, Y EOR IND, X EOR IND, Y ADC IND, X ADC IND, Y STA IND, X STA IND, Y LDA IND, X CLT JSR SP SET BBC 0, A BBS 1, A BBC 1, A BBS 2, A BBC 2, A BBS 3, A BBC 3, A BBS 4, A BBC 4, A BBS 5, A -- PHP -- 0001 1 BPL JSR ABS BMI -- BIT ZP -- COM ZP -- TST ZP -- STY ZP STY ZP, X LDY ZP LDY ZP, X CPY ZP -- CPX ZP -- CLC -- BIT ABS ASL CLB ORA ABS, X ABS, X 0, ZP AND ABS ROL ABS SEB 1, ZP 0010 2 PLP 0011 3 SEC ROL CLB LDM AND ZP ABS, X ABS, X 1, ZP JMP ABS -- JMP IND -- STY ABS -- LDY ABS EOR ABS LSR ABS SEB 2, ZP 0100 4 RTI STP PHA 0101 5 BVC -- MUL ZP, X -- RRF ZP -- LDX IMM CLI LSR CLB EOR ABS, X ABS, X 2, ZP ADC ABS ROR ABS SEB 3, ZP 0110 6 RTS PLA 0111 7 BVS SEI ROR CLB ADC ABS, X ABS, X 3, ZP STA ABS STA ABS, X LDA ABS STX ABS -- LDX ABS SEB 4, ZP CLB 4, ZP SEB 5, ZP 1000 8 BRA DEY TXA 1001 9 BCC LDY IMM BCS CPY IMM BNE CPX IMM BEQ TYA TXS 1010 A TAY TAX 1011 B JMP BBC LDA IND, Y ZP, IND 5, A CMP IND, X CMP IND, Y SBC IND, X SBC IND, Y WIT BBS 6, A BBC 6, A BBS 7, A BBC 7, A CLV TSX LDX CLB LDY LDA ABS, X ABS, X ABS, Y 5, ZP CPY ABS -- CPX ABS -- CMP ABS DEC ABS SEB 6, ZP 1100 C INY DEX 1101 D -- DIV ZP, X -- CLD -- DEC CLB CMP ABS, X ABS, X 6, ZP SBC ABS INC ABS SEB 7, ZP 1110 E INX NOP 1111 F SED -- INC CLB SBC ABS, X ABS, X 7, ZP : 3-byte instruction : 2-byte instruction : 1-byte instruction Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-133 APPENDIX 7540 Group 3.9 SFR memory map 3.9 SFR memory map 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 Pull-up control register (PULL) Port P1P3 control register (P1P3C) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) Timer A mode register (TAM) Timer A (low-order) (TAL) Timer A (high-order) (TAH) Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 MISRG Watchdog timer control register (WDTCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) A/D control register (ADCON) A/D conversion register (low-order) (ADL) A/D conversion register (high-order) (ADH) Serial I/O2 control register (SIO2CON) Serial I/O2 register (SIO2) Timer Y, Z mode register (TYZM) Prescaler Y (PREY) Timer Y secondary (TYS) Timer Y primary (TYP) Timer Y, Z waveform output control register (PUM) Prescaler Z (PREZ) Timer Z secondary (TZS) Timer Z primary (TZP) Prescaler 1 (PRE1) Timer 1 (T1) One-shot start register (ONS) Timer X mode register (TXM) Prescaler X (PREX) Timer X (TX) Timer count source set register (TCSS) Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-134 APPENDIX 7540 Group 3.10 Pin configurations 3.10 Pin configurations (Top view) 23 20 24 22 21 19 18 P07 P10/RXD1 P11/TXD1 P12/SCLK1/SCLK2 P13/SRDY1/SDATA2 P14/CNTR0 P20/AN0 P21/AN1 17 P06 P05 P04 P03/TXOUT P02/TZOUT P01/TYOUT P00/CNTR1 P37/INT0 25 26 27 28 29 30 31 32 M37540Mx-XXXGP M37540MxT-XXXGP M37540MxV-XXXGP M37540ExGP M37540E8T-XXXGP M37540E8V-XXXGP 16 15 14 13 12 11 10 9 P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0) VSS XOUT XIN 2 3 4 5 6 7 Package type: 32P6U-A Fig. 3.10.1 32P6U-A package pin configuration P22/AN2 P23/AN3 P24/AN4 P25/AN5 VREF RESET CNVSS VCC 1 8 Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-135 APPENDIX 7540 Group 3.10 Pin configurations (Top view) P12/SCLK1/SCLK2 P13/SRDY1/SDATA2 P14/CNTR0 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 VREF RESET CNVSS Vcc XIN XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 P11/TXD1 P10/RXD1 P07 P06 P05 P04 P03/TXOUT P02/TZOUT P01/TYOUT P00/CNTR1 P37/INT0 P36(LED6)/INT1 P35(LED5) P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0) Package type: 36P2R-A Fig. 3.10.2 36P2R-A package pin configuration M37540Mx-XXXFP M37540MxT-XXXFP M37540MxV-XXXFP M37540E8FP M37540E8T-XXXFP M37540E8V-XXXFP Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-136 APPENDIX 7540 Group 3.10 Pin configurations (Top view) P12/SCLK1/SCLK2 P13/SRDY1/SDATA2 P14/CNTR0 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 VREF RESET CNVSS VCC XIN XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P11/TXD1 P10/RXD1 P07 P06 P05 P04 P03/TXOUT P02/TZOUT P01/TYOUT P00/CNTR1 P37/INT0 P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0) Package type: 32P4B M37540Mx-XXXSP M37540ExSP Fig. 3.10.3 32P4B package pin configuration Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-137 APPENDIX 7540 Group 3.10 Pin configurations (Top view) P14/CNTR0 NC NC P20/AN0 P21/AN1 NC P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 NC NC VREF RESET CNVSS Vcc XIN XOUT VSS 1 2 3 4 5 6 7 42 41 40 39 38 37 36 8 9 10 11 12 13 14 15 16 17 18 19 20 21 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P13/SRDY1/SDATA2 P12/SCLK1/SCLK2 P11/TXD1 P10/RXD1 P07 P06 P05 P04 P03/TXOUT P02/TZOUT P01/TYOUT P00/CNTR1 NC P37/INT0 P36(LED6)/INT1 P35(LED5) P34(LED4) P33(LED3) P32(LED2) P31(LED1) P30(LED0) Outline 42S1M M37540RSS Fig. 3.10.4 42S1M package pin configuration Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-138 APPENDIX 7540 Group 3.11 Differences between 7540 Group and 7531 Group 3.11 Differences between 7540 Group and 7531 Group Table 3.11.1 shows the differences between 7540 Group and 7531 Group. Table 3.11.1 Differences between 7540 Group and 7531 Group (Performance overview) Parameter Number of basic instructions Memory sizes ROM RAM Input/Output ports Interrupt sources 36-pin version 16-bit timer 8-bit timer Serial I/O1 Clock generation circuit 32-pin version 7540 Group 71 (DIV, MUL instruction added) 16 to 32 K bytes 512 to 768 bytes Initial value: 0016 (Ports P0 and P3 pull-up Off) 14 sources, 14 vector (4 for external) 15 sources, 15 vector (5 for external) 1 (Timer A) 3 (Timer 1, X, Y, Z) Clock synchronous/UART Cecamic oscillator/ Quartz-crystal oscillator/ RC oscillation/ On-chip oscillator oscillation Oscillation stop detection circuit 1 3 (Timer 1, 2, X) UART only Cecamic oscillator/ Quartz-crystal oscillator/ RC oscillation 69 8 to 16 K bytes 256 to 384 bytes Initial value: FF16 (Ports P0 and P3 pull-up On) 11 sources, 8 vector (3 for external) 12 sources, 8 vector (4 for external) 7531 Group Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-139 APPENDIX 7540 Group 3.11 Differences between 7540 Group and 7531 Group Figure 3.11.1 shows the memory map of 7540 Group and 7531 Group. 7531 Group 000016 004016 SFR area 000016 004016 7540 Group SFR area Zero page 00FF16 010016 RAM (256/384 bytes) 00FF16 010016 RAM (512/768 bytes) XXXX16 Reserved area 044016 Not used YYYY16 ZZZZ16 Reserved ROM area (Common ROM area 128 bytes) PPPP16 Reserved area 044016 Not used QQQQ16 RRRR16 Reserved ROM area (Common ROM area 128 bytes) ROM ROM FF0016 FF0016 Special page FFEC16 Interrupt vector area FFFE16 FFFF16 Reserved ROM area FFDC16 FFFE16 FFFF16 Interrupt vector area Reserved ROM area RAM area RAM capacity (bytes) 256 384 ROM area ROM capacity (bytes) 8192 16384 Address YYYY16 E00016 C00016 Address ZZZZ16 E08016 C08016 Address XXXX16 013F16 01BF16 RAM area RAM capacity (bytes) 512 768 ROM area ROM capacity (bytes) 16384 32768 Address QQQQ16 C00016 800016 Address RRRR16 C08016 808016 Address PPPP16 023F16 033F16 Fig. 3.11.1 Memory map of 7540 Group and 7531 Group Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-140 APPENDIX 7540 Group 3.11 Differences between 7540 Group and 7531 Group Figure 3.11.2 shows the memory map of interrupt vector area of 7540 Group and 7531 Group. FFEC16 FFED16 FFEE16 FFEF16 FFF016 FFF116 FFF216 FFF316 FFF416 FFF516 FFF616 FFF716 FFF816 FFF916 FFFA16 FFFB16 FFFC16 FFFD16 BRK instruction interrupt CNTR0/A/D conversion interrupt Timer 2/Serial I/O2 interrupt Timer 1 interrupt Timer X/Key-on wakeup interrupt INT0 interrupt Serial I/O1 transmit/ INT1 (Note) interrupt Serial I/O1 receive interrupt Reset FFDC16 FFDD16 FFDE16 FFDF16 FFE016 FFE116 FFE216 FFE316 FFE416 FFE516 FFE616 FFE716 FFE816 FFE916 FFEA16 FFEB16 FFEC16 FFED16 FFEE16 FFEF16 FFF016 FFF116 FFF216 FFF316 FFF416 FFF516 FFF616 FFF716 FFF816 FFF916 FFFA16 FFFB16 FFFC16 FFFD16 BRK instruction interrupt Reserved area Timer 1 interrupt A/D conversion interrupt Serial I/O2 interrupt Timer A interrupt Timer Z interrupt Timer Y interrupt Timer X interrupt CNTR1 interrupt CNTR0 interrupt Key-on wakeup interrupt INT1 interrupt (Note) INT0 interrupt Serial I/O1 transmit interrupt Serial I/O1 receive interrupt Reset 7531 Group 7540 Group : Interrupts added in 7540 Group Note: The interrupt can be used only for the 36-pin version. Fig. 3.11.2 Memory map of interrupt vector area of 7540 Group and 7531 Group Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-141 APPENDIX 7540 Group 3.11 Differences between 7540 Group and 7531 Group Figure 3.11.3 shows the timer function of 7540 Group and 7531 Group. 7531 Group q Timer 1 (8-bit timer) * Timer mode 7540 Group q Timer 1 (8-bit timer) * Timer mode q Timer 2 (8-bit timer) * Timer mode q Timer X (8-bit timer) The number of timer increased Function expanded * Timer mode * Pulse output mode (inverted output port added) * Event counter mode * Pulse width measurement mode q Timer X (8-bit timer) * Timer mode * Pulse output mode * Event counter mode * Pulse width measurement mode q Timer Y (8-bit timer) * Timer mode * Programmable waveform generation mode Timer Y can be used for the timer Z count source. q Timer Z (8-bit timer) * Timer mode * Programmable waveform generation mode * Programmable one-shot generation mode * Programmable wait one-shot generation mode q Timer A (16-bit timer) * Timer mode * Period measurement mode * Event counter mode * Pulse width HL continuously measurement mode Fig. 3.11.3 Timer function of 7540 Group and 7531 Group Rev.2.00 Jun 21, 2004 REJ09B0018-0200Z 3-142 RENESAS 8-BIT CISC SINGLE-CHIP MICROCOMPUTER USER'S MANUAL 7540 Group Publication Data : Published by : Rev.1.00 Jan 01, 2002 Rev.2.00 Jun 21, 2004 Sales Strategic Planning Div. Renesas Technology Corp. (c) 2004. Renesas Technology Corp., All rights reserved. Printed in Japan. 7540 Group User's Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan |
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